PATENTSCOPE will be unavailable a few hours for maintenance reason on Tuesday 19.11.2019 at 4:00 PM CET
Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2007000683) BIPOLAR TRANSISTOR AND METHOD OP MANUFACTURING THE SAME
Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

CLAIMS:

1. A semiconductor device (10) with a substrate (11) and a semiconductor body (11) comprising a bipolar transistor with an emitter region (1) of a first conductivity type, a base region (2) of a second conductivity type opposite to the first conductivity type and a collector region (3) of said first conductivity type, which emitter region (1) comprises a mesa-shaped emitter connection region (IA) provided with spacers (4) and adjacent thereto a base connection region (2A) comprising a conductive region (2AA) of poly crystalline silicon, characterized in that the base connection region (2A) comprises a further conducting region (2AB), which is positioned between the conductive region (2AA) of poly crystalline silicon and the base region (2) and which is made of a material with respect to which the conducting region (2AA) of poly crystalline silicon is selectively etchable.

2. A semiconductor device (10) as claimed in claim 1, characterized in that the material of said further conductive region (2AB) is selectively etchable with respect to the material of the base region (2).

3. A semiconductor device (10) as claimed in claim 1 or 2, characterized in that said further conductive region (2AB) comprises a metal nitride, carbide, suicide or oxide.

4. A semiconductor device (10) as claimed in claim 1, 2 or 3, characterized in that the mesa-shaped emitter connection region has a T-shaped cross-section extending above an insulating region (5) formed on top of the conductive region (5).

5. A semiconductor device (10) as claimed in any one of the preceding claims, characterized in that the base region (2) comprises a highly doped subregion (2C) sunken in the semiconductor body (11), which, seen in projection, is adjacent to the outer side of the upper part of the emitter connection region (IA).

6 A semiconductor device (10) as claimed in any one of the preceding claims, characterized in that the device comprises field effect transistors in addition to bipolar transistors, the gate electrode of which field effect transistors has been formed by means of a layer structure as used also for forming said conductive region (2AA) of poly crystalline silicon and said further conductive region (2AB).

7. A semiconductor device as claimed in any one of the preceding claims, characterized in that said transistor is a heterojunction transistor.

8. A method of manufacturing a semiconductor device (10) with a substrate (12) and a semiconductor body (11) comprising a bipolar transistor with an emitter region (1) of a first conductivity type, a base region (2) of a second conductivity type opposite to the first conductivity type and a collector region (3) of said first conductivity type, which emitter region (1) is formed with a mesa-shaped emitter connection region (IA), which is isolated from a base connection region (2A) made up of a conductive region (2AA) of polycrystalline silicon by means of a spacer (4), characterized in that the base connection region (2A) is formed with a further conductive region (2AB) which is formed between the base region (2) and the conductive region (2AA) of polycrystalline silicon and for which a material is selected with respect to which the conductive region (2AA) is selectively etchable.

9. A method as claimed in claim 8, characterized in that a material which is selectively etchable with respect to the material of the base region (2) is selected for said further conductive region (2AB).

10. A method as claimed in claim 8 or 9, characterized in that the base region (2) is formed at the surface of the semiconductor body (11) and in that a conductive layer (2AA) of polycrystalline silicon is deposited on a further conductive layer (2AB) formed on the surface of the semiconductor body (11), after which an opening (6) is etched in said conductive layer (2AA) by means of an etchant that is selective to said further conductive layer (2AB).

11. A method as claimed in claim 10, characterized in that after the opening (6) in the conductive layer (2AA) has been formed, said further conductive layer (2AB) is etched therein by means of an etchant that is selective to the base region (2).

12. A method as claimed in claim 11, characterized in that after the spacer (4) has been formed against the walls of the opening (6) and on a part of the bottom of the opening (6) that joins said walls, an emitter connection region (IA) of poly crystalline silicon is formed in said opening (6).

13. A method as claimed in claim 12, characterized in that the emitter connection region (IA) is formed with a T-shaped cross-section and arranged to extend beside the opening above an insulating region (5) present on top of the conductive layer (2AA).

14. A method as claimed in claim 13, characterized in that the base region (2) is provided with a more highly doped subregion (2C) which, seen in projection, is adjacent to the outer side of the emitter connection region (IA).