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1. WO2006127751 - ELECTRICALLY ISOLATED CMOS DEVICE

Publication Number WO/2006/127751
Publication Date 30.11.2006
International Application No. PCT/US2006/019989
International Filing Date 23.05.2006
IPC
H01L 29/76 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
H01L 29/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
CPC
H01L 21/761
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
761PN junctions
H01L 21/823878
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8238Complementary field-effect transistors, e.g. CMOS
823878isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
H01L 21/823892
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8238Complementary field-effect transistors, e.g. CMOS
823892with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
H01L 27/0928
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
085including field-effect components only
088the components being field-effect transistors with insulated gate
092complementary MIS field-effect transistors
0928comprising both N- and P- wells in the substrate, e.g. twin-tub
H01L 29/78
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
Applicants
  • AMALFI SEMICONDUCTOR, INC. [US]/[US] (AllExceptUS)
  • SZETO, Clement [US]/[US] (UsOnly)
  • WOO, Chong [US]/[US] (UsOnly)
Inventors
  • SZETO, Clement
  • WOO, Chong
Agents
  • DAVIS, Paul
Priority Data
60/683,97623.05.2005US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ELECTRICALLY ISOLATED CMOS DEVICE
(FR) PROCEDE D'ATTENUATION DE LA PENETRATION DE BRUITS DE SUBSTRAT DANS DES CIRCUITS SENSIBLES
Abstract
(EN)
A CMOS device includes a p-type substrate (12) and an isolated PWeIl region (24) An isolation region has an NWeIl region (18,22) abutting a perimeter of the PWeIl region The isolation region includes a DNWeIl region (20) positioned below the PWeIl region and an NWeIl region The NWeIl region (22) forms a sidewall of a tub and the DNWeIl region (20) forms a bottom of the tub The tub (18,20,22) is an n-type region that physically and electrically isolates an enclosed PWeIl region (24) from the p-type substrate (12) A NTN region (26) is formed in the p- type substrate and at least partially abuts an outer perimeter of the NWeIl region The NTN region (26) is defined as a non-PWell and a non-NWell region The NTN region (26) enhances electrical isolation of the circuits inside the PWeIl region from circuits outside of the PWeIl region In one embodiment, the high-frequency performance of an NMOSFET inside the isolated PWeIl is improved because of the reduced sidewall capacitance with the NTN region.
(FR)
Cette invention concerne un dispositif CMOS comprenant un substrat dopé P et une région de puits dopée P isolée. Une région d'isolation comporte une région de puits dopé N touchant la région de puits dopé P. Cette région d'isolation comprend une région de puits dopé DN située sous la région de puits dopé P et sous une région de puits dopée N. La région de puits dopée N forme une paroi latérale de cuvette et la région de puits dopée DN le fond de la cuvette. La cuvette est constituée par une région de type n qui isole physiquement et électriquement la région de puits dopée P fermée du substrat de type p. Une région NTN est formée dans le substrat de type P et touche au moins partiellement le périmètre extérieur de la région de puits dopée N. La région NTN est définie comme une région de non-puits P et de non-puits N. Ladite région NTN améliore l'isolement électrique des circuits à l'intérieur de la région de puits dopé P par rapport aux circuits situés hors de cette même région. Dans un mode de réalisation, les performances haute fréquence d'un NMOSFET à l'intérieur du puits dopé P isolé se trouvent améliorées compte tenu de la capacitance réduite de la paroi avec la région NTN.
Also published as
EP6771003
Latest bibliographic data on file with the International Bureau