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1. WO2006127589 - NANOPARTICLES IN A FLASH MEMORY USING CHAPERONIN PROTEINS

Publication Number WO/2006/127589
Publication Date 30.11.2006
International Application No. PCT/US2006/019713
International Filing Date 22.05.2006
Chapter 2 Demand Filed 05.12.2006
IPC
H01L 29/423 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
CPC
B82Y 10/00
BPERFORMING OPERATIONS; TRANSPORTING
82NANOTECHNOLOGY
YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
10Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
H01L 29/40114
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
401Multistep manufacturing processes
4011for data storage electrodes
40114the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
H01L 29/42332
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
42324Gate electrodes for transistors with a floating gate
42332with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
H01L 51/0093
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
0032Selection of organic semiconducting materials, e.g. organic light sensitive or organic light emitting materials
0093Biomolecules or bio-macromolecules, e.g. proteines, ATP, chlorophyl, beta-carotene, lipids, enzymes
Applicants
  • BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM [US]/[US] (AllExceptUS)
  • MAO, Chuanbin [CN]/[US] (UsOnly)
  • TANG, Shan [CN]/[US] (UsOnly)
  • BANERJEE, Sanjay [US]/[US] (UsOnly)
Inventors
  • MAO, Chuanbin
  • TANG, Shan
  • BANERJEE, Sanjay
Agents
  • GARSSON, Ross, Spencer
Priority Data
60/683,60923.05.2005US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) NANOPARTICLES IN A FLASH MEMORY USING CHAPERONIN PROTEINS
(FR) NANOPARTICULES DANS UNE MEMOIRE FLASH UTILISANT DES PROTEINES APPELEES CHAPERONINE
Abstract
(EN)
A method for fabricating a flash memory device where the flash memory device includes a substantially uniform size and spatial distribution of nanoparticles on a tunnel oxide layer to form a floating gate. The flash memory device may be fabricated by defining active areas in a substrate and forming an oxide layer on the substrate. A self-assembled protein lattice may be formed on top of the oxide layer where the self-assembled protein lattice includes a plurality of molecular chaperones. The cavities of the chaperones may provide confined spaces where nanocrystals can be trapped thereby forming an ordered nanocrystal lattice. A substantially uniform distribution of nanocrystals may be formed on the oxide layer upon removal of the self-assembled protein lattice such as through high temperature annealing.
(FR)
L'invention concerne un procédé de fabrication d'une mémoire flash de taille sensiblement uniforme présentant une distribution spatiale de nanoparticules sur une couche d'oxyde tunnel afin de former une grille flottante. La mémoire flash peut être fabriquée en définissant des zones actives dans un substrat et en formant une couche d'oxyde sur le substrat. Un réseau de protéines autoassemblées comprenant une pluralité de chaperons moléculaires peut-être formé sur la couche d'oxyde. Les cavités des chaperons peuvent former des espaces confinés dans lesquels des nanocristaux peuvent être piégés de manière à former un réseau nanocristallin ordonné. Une distribution sensiblement uniforme de nanocristaux peut être formée sur la couche d'oxyde, une fois le réseau de protéines autoassemblées supprimé, notamment par recuit à température élevée.
Also published as
EP6770826
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