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1. WO2006127495 - METHODS AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A DISABLED SOI CIRCUIT

Publication Number WO/2006/127495
Publication Date 30.11.2006
International Application No. PCT/US2006/019534
International Filing Date 19.05.2006
IPC
H03K 19/00 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K 17/16 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
17Electronic switching or gating, i.e. not by contact-making and -breaking
16Modifications for eliminating interference voltages or currents
CPC
H03K 19/0016
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0008Arrangements for reducing power consumption
0016by using a control or a clock signal, e.g. in order to apply power supply
Applicants
  • SONY COMPUTER ENTERTAINMENT INC. [JP]/[JP] (AllExceptUS)
  • INTERNATIONAL BUSINESS MACHINES CORPORATION [US]/[US] (AllExceptUS)
  • TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. [US]/[US] (AllExceptUS)
Inventors
  • YOSHIHARA, Hiroshi
  • DHONG, Sang, Hoo
  • TAKAHASHI, Osamu
  • NAKAZATO, Takaaki
Agents
  • DERNIER, Matthew, B.
Priority Data
11/137,23425.05.2005US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHODS AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A DISABLED SOI CIRCUIT
(FR) PROCEDES ET APPAREIL POUR REDUIRE LE COURANT DE FUITE DANS UN CIRCUIT SOI DESACTIVE
Abstract
(EN)
Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially- equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on- insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node .
(FR)
La présente invention concerne des procédés et un appareil pour activer un circuit numérique en polarisant au moins un transistor de commutation ON de manière qu'un potentiel de tension d'un noeud de masse virtuel soit sensiblement égal à un potentiel de tension d'un noeud de masse pour une alimentation du circuit numérique. Le circuit numérique est mis en oeuvre en utilisant une pluralité de transistors dans un dispositif silicium sur isolant (SOI), au moins certains des transistors étant référencés sur le noeud de masse virtuel, puis en désactivant le circuit numérique par polarisation d'une borne de grille du transistor de commutation en dessous du potentiel de tension du noeud de masse.
Also published as
EP6760211
Latest bibliographic data on file with the International Bureau