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Pub. No.:    WO/2006/126301    International Application No.:    PCT/JP2005/023690
Publication Date: 30.11.2006 International Filing Date: 19.12.2005
H03G 3/10 (2006.01)
Applicants: NIIGATA SEIMITSU CO., LTD. [JP/JP]; 5-13, Nishishiro-cho 2-chome Jyoetsu-shi, Niigata 9430834 (JP) (For All Designated States Except US).
RICOH CO., LTD. [JP/JP]; 1-3-6 Nakamagome, Ota-ku, Tokyo 1438555 (JP) (For All Designated States Except US).
ISHIGURO, Kazuhisa [JP/JP]; (JP) (For US Only)
Inventors: ISHIGURO, Kazuhisa; (JP)
Agent: TACHIBANA, Kazuyuki; Hanzomon-First-Bldg. 1F, 1-4, Kojimachi, Chiyoda-ku, Tokyo 1020083 (JP)
Priority Data:
2005-149962 23.05.2005 JP
(JA) 自動利得制御回路
Abstract: front page image
(EN)A first MOS transistor (M1) and a second MOS transistor (M2) constitute a cascode amplifier. The second MOS transistor (M2) is in a differential connection with a gain control MOS transistor (M4), which has its gate supplied with an AGC control voltage (VAGC), and it is arranged that the device area ratio of the second MOS transistor (M2) to the gain control MOS transistor (M4) is one to N (where N ≥ 1). In this way, even in a region where the AGC control voltage (VAGC) is small, abrupt variations of the gain can be suppressed, while the drain current of the first MOS transistor (M1) can be kept constant independently of the gain control.
(FR)Premier transistor MOS (M1) et second transistor MOS (M2) constituant un amplificateur cascode. Le second transistor MOS (M2) est dans une connexion différentielle avec un transistor MOS de commande de gain (M4), qui a sa porte alimentée avec une tension de commande AGC (VAGC), et il est agencé de sorte que le rapport de zone de dispositif du second transistor MOS (M2) au transistor MOS de commande de gain (M4) est de un à N (où N ≥ 1). De cette manière, même dans une région où la tension de commande AGC (VAGC) est faible, des variations brutales du gain peuvent être supprimées pendant que le courant de drain du premier transistor MOS (M1) peut être maintenu constant indépendamment de la commande de gain.
(JA) カスコード増幅器を構成する第1のMOSトランジスタM1および第2のMOSトランジスタM2のうち、第2のMOSトランジスタM2に対して利得制御用MOSトランジスタM4を差動接続し、利得制御用MOSトランジスタM4のゲートにAGC制御電圧VAGCを供給するようにするとともに、第2のMOSトランジスタM2および利得制御用MOSトランジスタM4のデバイス面積比が1:N(N≧1)となるようにすることにより、AGC制御電圧VAGCが小さい領域においても、利得が急激に変わることを抑制できるようにするとともに、第1のMOSトランジスタM1のドレイン電流を利得制御に関係なく一定とすることができるようにする。
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)