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Machine translation
1. (WO2006118994) MULTI-CHIP MODULE AND METHOD OF MANUFACTURE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2006/118994    International Application No.:    PCT/US2006/016172
Publication Date: 09.11.2006 International Filing Date: 26.04.2006
IPC:
H01L 21/98 (2006.01), H01L 25/065 (2006.01)
Applicants: SPANSION LLC [US/US]; One AMD Place, Mail Stop 68, P.O. Box 3453, Sunnyvale, CA 94088-3453 (US) (For All Designated States Except US).
FONG, Ying, Lye [MY/US]; (US) (For US Only).
KEE, Cheng, Sim [MY/MY]; (MY) (For US Only).
LEE, Lay, Hong [MY/MY]; (MY) (For US Only).
BIN ABU-HASSAN, Mohammed Suhaizal [MY/MY]; (MY) (For US Only)
Inventors: FONG, Ying, Lye; (US).
KEE, Cheng, Sim; (MY).
LEE, Lay, Hong; (MY).
BIN ABU-HASSAN, Mohammed Suhaizal; (MY)
Agent: JAIPERSHAD, Rajendra; One AMD Place, Mail Stop 68, P.O. Box 3453, Sunnyvale, CA 94088-3453 (US)
Priority Data:
11/125,396 04.05.2005 US
Title (EN) MULTI-CHIP MODULE AND METHOD OF MANUFACTURE
(FR) MODULE MULTI-PUCE ET PROCEDE DE FABRICATION ASSOCIE
Abstract: front page image
(EN)A multi-chip module (10) and a method for manufacturing the multi-chip module (10) that mitigates wire breakage. A first semiconductor chip (40) is mounted and wirebonded to a support substrate (12). A spacer (50) is coupled to the first semiconductor chip (40). A support material (60) is disposed on the spacer (50) and a second semiconductor chip (64) is positioned on the support material (60). The second semiconductor chip (64) is pressed into the support material (60) squeezeing it into a region adjacent the spacer (50) and between the first (40) and second (64) semiconductor chips. Alternatively, the support material (60) is disposed on the first semiconductor chip (40) and a die attach material (62) is disposed on the spacer (50). The second semiconductor chip (64) is pressed into the die attach material (62) and the support material (60), squeezing a portion of the support material (60) over the spacer edges (53, 55). Wirebonds are formed between the support substrate (12) and the first (40) and second (64) semiconductor chips.
(FR)L'invention concerne un module multi-puce (10) et un procédé de fabrication de celui-ci (10) modérant la rupture de fil. Une première puce semi-conductrice (40) est montée sur un substrat support et liée par des fils à celui-ci (12). Un espaceur (50) est couplé à la première puce semi-conductrice (40). Un matériau support (60) est disposé sur l'espaceur (50) et une seconde puce semi-conductrice (64) est positionnée sur le matériau support (60). La seconde puce semi-conductrice (64) est pressé dans le matériau support (60), comprimant celui-ci dans une région adjacente à l'espaceur (50) et entre les première (40) et seconde (64) puces semi-conductrices. Dans un autre mode de réalisation, le matériau support (60) est disposé sur la première puce semi-conductrice (40) et un matériau de fixation de matrice (62) est disposé sur l'espaceur (50). La seconde puce semi-conductrice (64) est pressé dans le matériau de fixation de matrice (62) et le matériau support (60), comprimant une partie du matériau support (60) sur les bords de l'espaceur (53, 55). Des connexions au moyen de fils sont formées entre le substrat support (12) et les première (40) et seconde (64) puces semi-conductrices.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)