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1. WO2006117747 - 12C SLAVE DEVICE WITH PROGRAMMABLE WRITE-TRANSACTION CYCLES

Publication Number WO/2006/117747
Publication Date 09.11.2006
International Application No. PCT/IB2006/051360
International Filing Date 01.05.2006
IPC
G06F 3/147 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
14Digital output to display device
147using display panels
G09G 3/04 2006.1
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
04for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments
G09G 3/20 2006.1
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
CPC
G06F 13/4291
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
4282on a serial bus, e.g. I2C bus, SPI bus
4291using a clocked protocol
Applicants
  • KONINKLIJKE PHILIPS ELECTRONICS, N.V. [NL]/[NL] (AllExceptUS)
  • DESHPANDE, Amrita [US]/[US] (UsOnly)
  • ANDERSON, Alma [US]/[US] (UsOnly)
  • IRAZABAL, Jean-Marc [US]/[US] (UsOnly)
  • BLOZIS, Stephen [US]/[US] (UsOnly)
  • BOOGAARDS, Paul [US]/[US] (UsOnly)
Inventors
  • DESHPANDE, Amrita
  • ANDERSON, Alma
  • IRAZABAL, Jean-Marc
  • BLOZIS, Stephen
  • BOOGAARDS, Paul
Agents
  • ZAWILSKI, Peter
Priority Data
60/676,36029.04.2005US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) 12C SLAVE DEVICE WITH PROGRAMMABLE WRITE-TRANSACTION CYCLES
(FR) DISPOSITIF 12 C ASSERVI A CYCLES DE TRANSACTION D'ECRITURE PROGRAMMABLES
Abstract
(EN) Consistent with one example embodiment, communications systems (100,300), using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable updating of slave device output banks sequentially or simultaneously. The communications system includes two or more slave devices and/or a slave device having two or more banks of output drivers (350,360). Each slave device receives serial data and provides a data word assembled from the serial data. A programmable register (380) in each slave device is programmed, using the communications protocol, to select one or more slave device configurations. Each of the two or more slave devices and/or two or more banks of output drivers updates either sequentially, or in coordination with other of the two or more slave devices and/or two or more banks of output drivers, based on each slave devices configuration selected by its progammable register.
(FR) Selon un mode de réalisation de l'invention, des systèmes de communication (100, 300) utilisant un bus de transfert de données sérielles présentant une ligne de données sérielles et une ligne d'horloge servant à mettre en oeuvre un protocole de communication, impliquent la mise à jour programmable séquentielle ou simultanée de blocs mémoire de sortie de dispositifs asservis. Le système de communication comprend au moins deux dispositifs asservis et/ou un dispositif asservi présentant au moins deux blocs mémoire de pilotes de sortie (350, 360). Chaque dispositif asservi reçoit des données sérielles et fournit un mot de données assemblé à partir des données sérielles. Un registre programmable (380) dans chaque dispositif asservi est programmé à l'aide du protocole de communication pour sélectionner au moins une configuration de dispositifs asservis. Chaque dispositif asservi et/ou bloc mémoire de pilotes de sortie est mis à jour séquentiellement ou en coordination avec l'autre dispositif asservi/bloc de mémoire de pilotes de sortie, sur la base de chaque configuration de dispositif asservi sélectionné par son registre programmable.
Related patent documents
EP6728100This application is not viewable in PATENTSCOPE because the national phase entry has not been published yet or the national entry is issued from a country that does not share data with WIPO or there is a formatting issue or an unavailability of the application.
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