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1. WO2006100632 - SIDE WALL PORE SEALING FOR LOW-K DIELECTRICS

Publication Number WO/2006/100632
Publication Date 28.09.2006
International Application No. PCT/IB2006/050846
International Filing Date 20.03.2006
IPC
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
CPC
H01L 21/76808
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76808involving intermediate temporary filling with material
H01L 21/76811
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76811involving multiple stacked pre-patterned masks
H01L 21/76814
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76814post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
H01L 21/76826
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
76826by contacting the layer with gases, liquids or plasmas
H01L 2221/1063
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2221Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
10Applying interconnections to be used for carrying current between separate components within a device
1005Formation and after-treatment of dielectrics
1052Formation of thin functional dielectric layers
1057in via holes or trenches
1063Sacrificial or temporary thin dielectric films in openings in a dielectric
Applicants
  • NXP B.V. [NL]/[NL] (AllExceptUS)
  • BESLING, Willem, Frederik, Adrianus [NL]/[FR] (UsOnly)
Inventors
  • BESLING, Willem, Frederik, Adrianus
Agents
  • PENNINGS, Johannes
Priority Data
05300202.822.03.2005EP
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SIDE WALL PORE SEALING FOR LOW-K DIELECTRICS
(FR) SCELLEMENT DES PORES DE LA PAROI LATERALE DE DIELECTRIQUES PRESENTANT UNE VALEUR K BASSE
Abstract
(EN)
A dual damascene process for forming conductive interconnects on an integrated circuit die. The process comprises providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric ('porogen') material (42) is applied to the side walls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16).
(FR)
Procédé de double damasquinage servant à créer des interconnexions conductrices sur un dé de circuit intégré. Ce procédé consiste à mettre en application une couche (16) de matériau diélectrique poreux présentant une valeur k ultrabasse (ULK) et dans lequel on pratique ensuite une ouverture d'interconnexion (30). On applique un matériau polymère (42) dégradable sous l'effet de la chaleur ('porogène') aux parois latérales de l'ouverture (30), de sorte que ce matériau porogène pénètre profondément dans le matériau diélectrique ULK poreux, ce qui permet d'en sceller les pores et d'en augmenter la densité. Une fois qu'un matériau conducteur (36) a été pourvu de l'ouverture (30) et repoli au moyen d'un polissage chimio-mécanique (CMP), la structure complète est soumise à une structure de durcissement afin de provoquer la décomposition et l'évaporation du matériau porogène (44) avec la couche diélectrique ULK (16), ce qui restitue la porosité de la couche diélectrique (16), ainsi que sa valeur k basse.
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