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1. WO2006098196 - PACKAGE EQUIPPED WITH SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING SAME

Publication Number WO/2006/098196
Publication Date 21.09.2006
International Application No. PCT/JP2006/304442
International Filing Date 08.03.2006
IPC
H01L 21/60 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
CPC
H01L 21/563
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
H01L 2224/0554
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
H01L 2224/05568
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
05568the whole external layer protruding from the surface
H01L 2224/05573
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05573Single external layer
H01L 2224/05611
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05601the principal constituent melting at a temperature of less than 400°C
05611Tin [Sn] as principal constituent
H01L 2224/05624
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05617the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
05624Aluminium [Al] as principal constituent
Applicants
  • 松下電器産業株式会社 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. [JP]/[JP] (AllExceptUS)
  • 白石 司 SHIRAISHI, Tsukasa (UsOnly)
  • 石丸 幸宏 ISHIMARU, Yukihiro (UsOnly)
  • 辛島 靖治 KARASHIMA, Seiji (UsOnly)
  • 中谷 誠一 NAKATANI, Seiichi (UsOnly)
  • 矢部 裕城 YABE, Hiroki (UsOnly)
Inventors
  • 白石 司 SHIRAISHI, Tsukasa
  • 石丸 幸宏 ISHIMARU, Yukihiro
  • 辛島 靖治 KARASHIMA, Seiji
  • 中谷 誠一 NAKATANI, Seiichi
  • 矢部 裕城 YABE, Hiroki
Agents
  • 前田 弘 MAEDA, Hiroshi
Priority Data
2005-07679817.03.2005JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) PACKAGE EQUIPPED WITH SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING SAME
(FR) BOITIER EQUIPE D’UNE PUCE A SEMI-CONDUCTEUR ET PROCEDE POUR LE PRODUIRE
(JA) 半導体チップを備えた実装体およびその製造方法
Abstract
(EN)
A highly reliable, high-productivity package equipped with a semiconductor chip, and a method for producing the same. In a package (100) comprising a semiconductor chip (10) and a mounting substrate (30), a plurality of element electrodes (12) are formed on the surface (10a) of the semiconductor chip (10) opposing the mounting substrate side, electrode terminals (32) respectively corresponding to the plurality of element electrodes (12), are formed on the mounting substrate (30), the electrode terminals (32) on the mounting substrate (30) and the element electrodes (12) are electrically connected collectively by solder bumps (17) formed in self assembly, an electrode pattern (20) not connected with the element electrodes (12) and the electrode terminals (32) is formed on the chip surface (10a) or the surface (35) of the mounting substrate (30) corresponding to the chip surface (10a), and solder (19) is accumulated on the electrode pattern (20).
(FR)
L’invention décrit un boîtier de fiabilité et productivité élevées équipé d’une puce à semi-conducteur, ainsi qu’un procédé permettant de le produire. Dans un boîtier (100) comprenant une puce à semi-conducteur (10) et un substrat de montage (30), une pluralité d’électrodes élémentaires (12) sont formées sur la surface (10a) de la puce à semi-conducteur (10) du côté opposé au côté du substrat de montage ; des bornes d’électrode (32) correspondant respectivement à la pluralité d’électrodes élémentaires (12) sont formées sur le substrat de montage (30), lesdites bornes d’électrode (32) et les électrodes élémentaires (12) étant électriquement raccordées par des billes de brasure (17) formées en auto-assemblage ; enfin, un schéma d’électrode (20) non raccordé aux électrodes élémentaires (12) et aux bornes des électrodes (32) est formé sur la surface de la puce (10a) ou sur la surface (35) du substrat de montage (30) correspondant à la surface de la puce (10a), de la brasure (19) étant accumulée sur le schéma d’électrode (20).
(JA)
not available
Also published as
EP6728761
Latest bibliographic data on file with the International Bureau