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1. WO2006095890 - SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Publication Number WO/2006/095890
Publication Date 14.09.2006
International Application No. PCT/JP2006/304831
International Filing Date 07.03.2006
IPC
H01L 21/8247 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8246Read-only memory structures (ROM)
8247electrically-programmable (EPROM)
H01L 27/115 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
H01L 29/788 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
788with floating gate
H01L 29/792 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
792with charge trapping gate insulator, e.g. MNOS-memory transistor
CPC
B82Y 10/00
BPERFORMING OPERATIONS; TRANSPORTING
82NANOTECHNOLOGY
YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
10Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
H01L 29/40117
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
401Multistep manufacturing processes
4011for data storage electrodes
40117the electrodes comprising a charge-trapping insulator
H01L 29/42332
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
42324Gate electrodes for transistors with a floating gate
42332with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
H01L 29/7881
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
788with floating gate
7881Programmable transistors with only two possible levels of programmation
Applicants
  • 日本電気株式会社 NEC Corporation [JP]/[JP] (AllExceptUS)
  • 多田 あゆ香 TADA, Ayuka [JP]/[JP] (UsOnly)
  • 渡辺 啓仁 WATANABE, Hirohito [JP]/[JP] (UsOnly)
  • 五十嵐 多恵子 IKARASHI, Taeko [JP]/[JP] (UsOnly)
  • 砂村 潤 SUNAMURA, Hiroshi [JP]/[JP] (UsOnly)
Inventors
  • 多田 あゆ香 TADA, Ayuka
  • 渡辺 啓仁 WATANABE, Hirohito
  • 五十嵐 多恵子 IKARASHI, Taeko
  • 砂村 潤 SUNAMURA, Hiroshi
Agents
  • 池田 憲保 IKEDA, Noriyasu
Priority Data
2005-06183607.03.2005JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF DE SEMI-CONDUCTEUR ET SON PROCEDE DE FABRICATION
(JA) 半導体装置およびその製造方法
Abstract
(EN)
In a memory cell (20) wherein a gate electrode (6) is formed on a p-type silicon substrate (1) via a silicon oxide film (3) and an n-type diffusion layer to be a source/drain region is formed within surface reagions of the silicon substrate (1) which are located on both sides of the gate electrode (6), an impurity to be a trap site (5) is contained in the silicon oxide film (3). A metal such as Al, Au and Ti is used as the impurity. The gate insulating film may be composed of the silicon oxide film (3) and another insulating film (4). The trap site (5) may be formed in the another insulating film (4) by doping. Alternatively, the interface between the silicon oxide film (3) and the another insulating film (4) may be mainly doped with the impurity. Consequently, there can be obtained a nonvolatile memory having good holding characteristics.
(FR)
Dans une cellule mémoire (20) dans laquelle une électrode de grille (6) est constituée sur un substrat de silicium de type p (1) par le biais d’un film d’oxyde de silicium (3), une couche de diffusion de type n destinée à servir de région source/drain est constituée à l’intérieur des zones de surface du substrat de silicium (1) situées des deux côtés de l’électrode de grille (6) ; une impureté fonctionnant comme un piège (5) est contenue dans le film d’oxyde de silicium (3). Un métal tel que Al, Au ou Ti est utilisé comme impureté. Le film isolant de grille peut être constitué du film d’oxyde de silicium (3) et d’un autre film isolant (4). Le piège (5) peut être constitué dans l’autre film isolant (4) par dopage. L’interface entre le film d’oxyde de silicium (3) et l’autre film isolant (4) peut également être principalement dopée avec l’impureté. On peut ainsi obtenir une mémoire non volatile possédant de bonnes caractéristiques de conservation.
(JA)
p型シリコン基板1にシリコン酸化膜3を介してゲート電極6を設け、ゲート電極6を挟むシリコン基板1の表面領域内にソース・ドレイン領域となるn型拡散層が形成されているメモリセル20は、シリコン酸化膜3内にトラップサイト5となる不純物が含まれている。不純物にはAl、Au、Tiなどの金属が用いられる。ゲート絶縁膜はシリコン酸化膜3と他の絶縁膜4とによって形成されていてもよい。トラップサイト5は他の絶縁膜4側にドープされていてもよい。また、シリコン酸化膜3と絶縁膜4との界面を中心としてドープされていてもよい。このようにして、保持特性のよい不揮発性メモリを提供する。
Also published as
EP6728947
Latest bibliographic data on file with the International Bureau