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1. WO2006095655 - SEMICONDUCTOR INTEGRATED CIRCUIT

Publication Number WO/2006/095655
Publication Date 14.09.2006
International Application No. PCT/JP2006/304122
International Filing Date 03.03.2006
IPC
H01L 21/3205 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/82 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 21/822 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
H01L 23/52 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
H01L 27/04 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
CPC
H01L 21/31053
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
31051Planarisation of the insulating layers
31053involving a dielectric removal step
H01L 21/7684
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
7684Smoothing; Planarisation
H01L 23/5222
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
5222Capacitive arrangements or effects of, or between wiring layers
H01L 23/528
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528Geometry or; layout of the interconnection structure
H01L 27/0203
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
0203Particular design considerations for integrated circuits
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applicants
  • 松下電器産業株式会社 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. [JP]/[JP] (AllExceptUS)
  • 川上 善之 KAWAKAMI, Yoshiyuki (UsOnly)
Inventors
  • 川上 善之 KAWAKAMI, Yoshiyuki
Agents
  • 前田 弘 MAEDA, Hiroshi
Priority Data
2005-06969611.03.2005JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR INTEGRATED CIRCUIT
(FR) CIRCUIT INTEGRE A SEMICONDUCTEUR
(JA) 半導体集積回路
Abstract
(EN)
In planarizing process of an LSI layout pattern, at the time of arranging dummy patterns, a plurality of dummy patterns (1) having an inclination angle of substantially 45 degrees to a signal wiring pattern (2) are arranged on a wiring layer whereupon the signal wiring pattern (2) is arranged. The dummy patterns (1) intersect with a signal wiring pattern (3) formed on other adjacent wiring layer above or below at an inclination angle of substantially 45 degrees. A plurality of dummy patterns (13) having an inclination angle of substantially 45 degrees to the signal wiring pattern (3) are arranged on the wiring layer of the signal wiring pattern (3). The dummy patterns (1, 13) on the two adjacent wiring layers intersect at an angle of substantially 90 degrees. Therefore, wiring capacity fluctuation is reduced and a wiring capacity fluctuation quantity is made uniform to a maximum extent.
(FR)
Dans le procédé destiné à rendre plan un motif d'implantation de circuit LSI, au moment de disposer des motifs fictifs, une pluralité de motifs fictifs (1) présentant un angle d'inclinaison d'essentiellement 45 degrés par rapport à un motif de câblage de signal (2) sont agencés sur une couche de câblage sur laquelle est disposé le motif de câblage de signal (2). Les motifs fictifs (1) coupent un motif de câblage de signal (3) formé sur une autre couche de câblage contiguë, au-dessus ou en dessous, avec un angle inclinaison d'essentiellement 45 degrés. Une pluralité de motifs fictifs (13) présentant un angle d'inclinaison d'essentiellement 45 degrés par rapport au motif de câblage de signal (3) sont disposés sur la couche de câblage du motif de câblage de signal (3). Les motifs fictifs (1, 13) sur les deux couches de câblage contiguës se coupent avec un angle d'essentiellement 90 degrés. Par conséquent, toute fluctuation de capacité de câblage est réduite et la valeur de fluctuation de capacité de câblage est rendue uniforme au maximum.
(JA)
 LSIレイアウトパターンの平坦化処理において、ダミーパターンを配置する場合に、信号配線パターン2が配置される配線層には、信号配線パターン2に対して略45度の傾斜角を持たせた複数のダミーパターン1が配置される。これ等のダミーパターン1は、上又は下に隣接する他の配線層に形成された信号配線パターン3に対しても略45度の傾斜角を持って交差する。前記信号配線パターン3の配線層には、この信号配線パターン3対して略45度の傾斜角を持たせた複数のダミーパターン13が配置される。前記隣接する2つの配線層のダミーパターン1、13は略90度の角度で交差する。従って、配線容量変動が低減されると共に、配線容量変動量が可能な限り均一化される。
Also published as
EP6715205
Latest bibliographic data on file with the International Bureau