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1. WO2006095602 - MOUNTING BODY AND METHOD FOR MANUFACTURING SAME

Publication Number WO/2006/095602
Publication Date 14.09.2006
International Application No. PCT/JP2006/303713
International Filing Date 28.02.2006
IPC
H01L 25/065 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
H01L 21/60 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 25/07 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
07the devices being of a type provided for in group H01L29/78
H01L 25/18 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
CPC
H01L 2224/16145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16135the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
16145the bodies being stacked
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/32145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32135the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
32145the bodies being stacked
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48225the item being non-metallic, e.g. insulating substrate with or without metallisation
48227connecting the wire to a bond pad of the item
Applicants
  • 松下電器産業株式会社 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. [JP]/[JP] (AllExceptUS)
  • 小松慎五 KOMATSU, Shingo (UsOnly)
  • 中谷誠一 NAKATANI, Seiichi (UsOnly)
  • 辛島靖治 KARASHIMA, Seiji (UsOnly)
  • 小島俊之 KOJIMA, Toshiyuki (UsOnly)
  • 北江孝史 KITAE, Takashi (UsOnly)
  • 山下嘉久 YAMASHITA, Yoshihisa (UsOnly)
Inventors
  • 小松慎五 KOMATSU, Shingo
  • 中谷誠一 NAKATANI, Seiichi
  • 辛島靖治 KARASHIMA, Seiji
  • 小島俊之 KOJIMA, Toshiyuki
  • 北江孝史 KITAE, Takashi
  • 山下嘉久 YAMASHITA, Yoshihisa
Agents
  • 特許業務法人池内・佐藤アンドパートナーズ IKEUCHI SATO & PARTNER PATENT ATTORNEYS
Priority Data
2005-06196307.03.2005JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) MOUNTING BODY AND METHOD FOR MANUFACTURING SAME
(FR) CORPS DE MONTAGE ET SON PROCEDE DE FABRICATION
(JA) 実装体及びその製造方法
Abstract
(EN)
A mounting body includes a multilayer semiconductor chip (20) wherein a plurality of semiconductor chips (10 (10a, 10b)) are stacked, and a mounting board (13) whereupon the multilayer semiconductor chip (20) is mounted. On each of the semiconductor chips (10 (10a, 10b) in the multilayer semiconductor chip (20), a plurality of element electrodes (12 (12a, 12b) are formed on chip surfaces (21 (21a, 21b) facing a side of a mounting substrate (13). On the mounting substrate (13), electrode terminals (14) are formed corresponding to each of element electrodes (12a, 12b). The electrode terminal (14) of the mounting substrate (13) and the element electrodes (12a, 12b) are electrically connected by solder bumps formed by collecting solder particles. Thus, the mounting body whereupon a stacked package is mounted can be easily manufactured.
(FR)
La présente invention concerne un corps de montage comprenant une puce de semi-conducteur multicouches (20), dans lequel une pluralité de puces de semi-conducteur (10 (10a, 10b)) est empilée et une plaque de montage (13) sur laquelle la puce de semi-conducteur multicouches (20) est montée. Sur chacune des puces de semi-conducteur (10 (10a, 10b)) dans la puce de semi-conducteur multicouches (20), une pluralité d’électrodes d’élément (12 (12a, 12b) est formée sur les surfaces des puces (21 (21a, 21b)) orientées vers un côté d’un substrat de montage (13). Sur le substrat de montage (13), des bornes d’électrodes (14) sont formées, qui correspondent à chacune des électrodes d’élément (12a, 12b). La borne d’électrode (14) du substrat de montage (13) et les électrodes d’élément (12a, 12b) sont raccordées électriquement par des perles de soudure formées en collectant des particules de soudure. Ainsi, le corps de montage sur lequel un boîtier empilé est monté peut être fabriqué facilement.
(JA)
 複数の半導体チップ10(10a、10b)が積層された積層半導体チップ20と、積層半導体チップ20が実装された実装基板13を含み、積層半導体チップ20における各半導体チップ10(10a、10b)には、実装基板13側に面するチップ表面21(21a、21b)に複数の素子電極12(12a、12b)が形成されており、実装基板13には、複数の素子電極(12a、12b)のそれぞれに対応して、電極端子14が形成されており、実装基板13の電極端子14と、素子電極(12a、12b)とは、半田粒子が集合して形成された半田バンプによって電気的に接続されている。これによりスタックドパッケージが実装された実装体を容易に製造できる。
Also published as
EP6714850
Latest bibliographic data on file with the International Bureau