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1. WO2006095389 - MAGNETIC MEMORY AND READ/WRITE METHOD THEREOF

Publication Number WO/2006/095389
Publication Date 14.09.2006
International Application No. PCT/JP2005/003740
International Filing Date 04.03.2005
IPC
H01L 27/105 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
G11C 11/15 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
14using thin-film elements
15using multiple magnetic layers
H01L 43/08 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
08Magnetic-field-controlled resistors
CPC
G11C 11/15
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
14using thin-film elements
15using multiple magnetic layers
G11C 2213/75
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2213Indexing scheme relating to G11C13/00 for features not covered by this group
70Resistive array aspects
75Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
H01L 27/228
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
22including components using galvano-magnetic effects, e.g. Hall effects; using similar magnetic field effects
222Magnetic non-volatile memory structures, e.g. MRAM
226comprising multi-terminal components, e.g. transistors
228of the field-effect transistor type
Applicants
  • 富士通株式会社 FUJITSU LIMITED [JP]/[JP] (AllExceptUS)
  • 青木 正樹 AOKI, Masaki [JP]/[JP] (UsOnly)
Inventors
  • 青木 正樹 AOKI, Masaki
Agents
  • 北野 好人 KITANO, Yoshihito
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) MAGNETIC MEMORY AND READ/WRITE METHOD THEREOF
(FR) MEMOIRE MAGNETIQUE ET PROCEDE DE LECTURE/ECRITURE ASSOCIE
(JA) 磁気メモリ装置並びにその読み出し方法及び書き込み方法
Abstract
(EN)
A magnetic memory comprising a first signal line (BL) and a second signal line (/BL) extending in the column direction, a third signal line (WL) extending in the row direction, a memory cell having of a first parallel connection of a first magnetoresistive element (MTJ1) and a first select transistor (Tr1) provided in the intersection area of the first and third signal lines and connected with the first signal line at one end side thereof, and a second parallel connection of a second magnetoresistive element (MTJ2) and a second select transistor (Tr2) provided in the intersection area of the second and third signal lines and connected with the second signal line at one end side thereof, and a read circuit connected with the first and second signal lines for reading out information stored in the memory cell based on the voltages of the first and second signal lines.
(FR)
La présente invention se rapporte à une mémoire magnétique, qui comprend : une première ligne de signal (BL) et une deuxième ligne de signal (/BL) s'étendant dans le sens des colonnes ; une troisième ligne de signal (WL) s'étendant dans le sens des rangées ; une cellule de mémoire, qui possède une première connexion parallèle composée d'un premier élément magnétorésistif (MTJ1) et d'un premier transistor de sélection (TR1), qui est située dans la zone d'intersection des première et troisième lignes de signal et est reliée à la première ligne de signal à une extrémité de cette dernière, et une seconde connexion parallèle composée d'un second élément magnétorésistif (MTJ2) et d'un second transistor de sélection (Tr2), qui est située dans la zone d'intersection des deuxième et troisième lignes de signal et est reliée à la deuxième ligne de signal à une extrémité de cette dernière ; et un circuit de lecture, qui est relié aux première et deuxième lignes de signal et est destiné à lire des informations stockées dans la cellule de mémoire sur la base de la tension des première et deuxième lignes de signal.
(JA)
 列方向に延在する第1の信号線(BL)及び第2の信号線(/BL)と、行方向に延在する第3の信号線(WL)と、第1の信号線と第3の信号線との交差領域に設けられた第1の磁気抵抗効果素子(MTJ)と第1の選択トランジスタ(Tr)とが並列に接続されてなり、その一端側が第1の信号線に接続された第1の並列接続体と、第2の信号線と第3の信号線との交差領域に設けられた第2の磁気抵抗効果素子(MTJ)と第2の選択トランジスタ(Tr)とが並列に接続されてなり、その一端側が第2の信号線に接続された第2の並列接続体とを有するメモリセルと、第1の信号線及び第2の信号線に接続され、第1の信号線及び第2の信号線の電圧に基づいてメモリセルに記憶された情報を読み出す読み出し回路とを有する。
Also published as
EP5720012
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