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1. WO2006093635 - METHOD AND CIRCUIT FOR THE DETECTION OF SOLDER-JOINT FAILURES IN A DIGITAL ELECTRONIC PACKAGE

Publication Number WO/2006/093635
Publication Date 08.09.2006
International Application No. PCT/US2006/004335
International Filing Date 08.02.2006
IPC
G01R 1/073 2006.01
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
1Details of instruments or arrangements of the types covered by groups G01R5/-G01R13/122
02General constructional details
06Measuring leads; Measuring probes
067Measuring probes
073Multiple probes
G01R 31/28 2006.01
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
CPC
G01R 31/2884
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
2851Testing of integrated circuits [IC]
2884using dedicated test connectors, test elements or test circuits on the IC under test
G01R 31/312
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
302Contactless testing
312by capacitive methods
G01R 31/71
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
66Testing of connections, e.g. of plugs or non-disconnectable joints
70Testing of connections between components and printed circuit boards
71Testing of solder joints
Applicants
  • RIDGETOP GROUP, INC. [US]/[US] (AllExceptUS)
  • VERMEIRE, Bert [BE]/[US] (UsOnly)
  • HOFMEISTER, James [US]/[US] (UsOnly)
  • SPUHLER, Philipp [US]/[US] (UsOnly)
Inventors
  • VERMEIRE, Bert
  • HOFMEISTER, James
  • SPUHLER, Philipp
Agents
  • GIFFORD, Eric
Priority Data
11/325,07604.01.2006US
60/657,10128.02.2005US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD AND CIRCUIT FOR THE DETECTION OF SOLDER-JOINT FAILURES IN A DIGITAL ELECTRONIC PACKAGE
(FR) PROCEDE ET CIRCUIT DE DETECTION DE DEFAUTS DE JONCTIONS SOUDEES DANS UN BOITIER ELECTRONIQUE NUMERIQUE
Abstract
(EN)
The solder-joint integrity of digital electronic packages, such as FPGAs (120) or microcontrollers that have internally connected input /output buffers (146a/b, 148a/b), is evaluated by applying a time-varying voltage through one or more solder- joint networks (153a) to charge a charge- storage component (156). Each network includes an I/O buffer (146a) on the die (138) in the package and a solder-joint connection (124), typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder- joint network, hence the voltage measured across the charge-storage component is an indicator of the integrity of the solder-joint network.
(FR)
La présente invention concerne l'évaluation de l'intégrité des jonctions soudées de boîtiers électroniques numériques tels que les matrices prédiffusées programmables par l'utilisateur (120) ou des contrôleurs microprogrammés comportant des tampons d'E/S connectés en interne (146a/b, 148a/b). A cet effet, on applique une tension variant en durée via un ou plusieurs réseaux de jonctions soudées (153a) de façon à charger un composant mémoire à charge (156). Chaque réseau comporte un tampon d'E/S (146) sur la micro-plaquette (138) dans le boîtier, et une connexion par jonctions soudées (124), généralement à raison d'une ou de plusieurs de ces connexions à l'intérieur du boîtier et entre le boîtier et une plaque. La constante de temps de charge du composant est proportionnelle à la résistance du réseau à jonctions soudées, la tension mesurée aux bornes du composant à mémoire à charge est un indicateur de l'intégrité du réseau à jonctions soudées.
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