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1. WO2006093629 - NON-VOLATILE AND STATIC RANDOM ACCESS MEMORY CELLS SHARING THE SAME BITLINES

Publication Number WO/2006/093629
Publication Date 08.09.2006
International Application No. PCT/US2006/004155
International Filing Date 07.02.2006
IPC
G11C 11/34 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
CPC
G11C 14/00
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
14Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
Applicants
  • O2IC, INC. [US]/[US] (AE, AG, AL, AM, AT, AU, AZ, BA, BB, BE, BF, BG, BJ, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GW, HR, HU, ID, IE, IL, IN, IS, IT, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, MG, MK, ML, MN, MR, MW, MX, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SI, SK, SL, SM, SN, SY, SZ, TD, TG, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, YU, ZA, ZM, ZW)
  • CHOI, David, S. [US]/[US] (UsOnly)
  • KWON, Eui, Pil [KR]/[US] (UsOnly)
  • CHOI, Kyu, Hyun [US]/[US] (UsOnly)
Inventors
  • CHOI, David, S.
  • KWON, Eui, Pil
  • CHOI, Kyu, Hyun
Agents
  • TABIBI, Ardeshir
Priority Data
11/067,31325.02.2005US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) NON-VOLATILE AND STATIC RANDOM ACCESS MEMORY CELLS SHARING THE SAME BITLINES
(FR) CELLULES DE MEMOIRE NON VOLATILE ET A ACCES SELECTIF STATIQUE PARTAGEANT LES MEMES LIGNES BINAIRES
Abstract
(EN)
A memory cell structure includes non-volatile as well as SRAM memory cells that share the same bitline and operate differentially. The SRAM cell includes first and second MOS transistors that are coupled to the same true and complementary bit lines that the non-volatile memory cells are coupled to. The non-volatile memory cells are erased prior to being programmed. Programming of the non-volatile memory cells may be carried out via hot-electron injection or Fowler-Nordheim tunneling. Data stored in the non-volatile memory cells may be transferred to the SRAM cell. The differential reading and writing of data reduces over-erase of the non-volatile devices.
(FR)
La présente invention concerne une structure de cellule de mémoire comportant des cellules de mémoire non volatile et à accès sélectif statique (SRAM) qui partagent la même ligne binaire et opèrent de façon différente. La cellule SRAM comprend un premier et un second transistor MOS, couplés aux mêmes lignes binaires réelles et complémentaires que celles auxquelles sont couplées les cellules de mémoire non volatile. Les cellules de mémoire non volatile sont effacées avant d’être programmées. La programmation des cellules de mémoire non volatile peut être effectuée par le biais d’une injection d’électrons chauds ou effet tunnel de Fowler-Nordheim. Les données stockées dans les cellules de mémoire non volatile peuvent être transférées dans la cellule SRAM. La différence de lecture et d’écriture des données réduit l'effacement excessif des dispositifs non volatiles.
Also published as
EP06720377
EP6720377
Latest bibliographic data on file with the International Bureau