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1. WO2006093272 - WIRING SUBSTRATE, MANUFACTURING METHOD THEREOF, AND RESIN BODY SURFACE TREATMENT METHOD

Publication Number WO/2006/093272
Publication Date 08.09.2006
International Application No. PCT/JP2006/304103
International Filing Date 03.03.2006
IPC
H05K 3/38 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
38Improvement of the adhesion between the insulating substrate and the metal
H05K 3/06 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
02in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
06the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
H05K 3/18 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
10in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
18using precipitation techniques to apply the conductive material
H05K 3/46 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multi-layer circuits
CPC
H05K 2203/1152
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2203Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
11Treatments characterised by their effect, e.g. heating, cooling, roughening
1152Replicating the surface structure of a sacrificial layer, e.g. for roughening
H05K 3/381
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
38Improvement of the adhesion between the insulating substrate and the metal
381by special treatment of the substrate
H05K 3/4661
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multilayer circuits
4644by building the multilayer layer by layer, i.e. build-up multilayer circuits
4661Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
Applicants
  • 株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP]/[JP] (AllExceptUS)
  • 平山 克郎 HIRAYAMA, Katsuro [JP]/[JP] (UsOnly)
Inventors
  • 平山 克郎 HIRAYAMA, Katsuro
Agents
  • 深見 久郎 FUKAMI, Hisao
Priority Data
2005-06112404.03.2005JP
2005-24983030.08.2005JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) WIRING SUBSTRATE, MANUFACTURING METHOD THEREOF, AND RESIN BODY SURFACE TREATMENT METHOD
(FR) SUBSTRAT DE CONNEXION, PROCÉDÉ DE FABRICATION IDOINE ET PROCÉDÉ DE TRAITEMENT DE SURFACE DE CORPS DE RÉSINE
(JA) 配線基板およびその製造方法ならびに樹脂体の表面加工方法
Abstract
(EN)
A wiring substrate includes a resin insulation layer (2) having a main surface and a wiring layer (12) arranged in contact with the main surface. The region of the main surface in contact with the wiring layer (12) has a surface roughness Ra not greater than 1.0 μm. Preferably, the region of the main surface in contact with the wiring layer (12) has a surface roughness Ra not greater than 0.3 μm. Preferably, the wiring substrate includes a core substrate (1) and the resin insulation layer (2) is arranged so as to cover the surface of the core substrate (1).
(FR)
L’invention concerne un substrat de connexion comprenant une couche d’isolation de résine (2) ayant une surface principale et une couche de câblage (12) au contact de la surface principale. La région de la surface principale au contact de la couche de câblage (12) possède une rugosité de surface Ra ne dépassant pas 1,0 µm. De préférence, la région de la surface principale au contact de la couche de câblage (12) possède une rugosité de surface Ra ne dépassant pas 0,3 µm. De préférence, le substrat de connexion contient un substrat central (1) et la couche d’isolation de résine (2) recouvre la surface du substrat central (1).
(JA)
 配線基板は、主表面を有する樹脂絶縁層(2)と、前記主表面に接して配置された配線層(12)とを備え、前記主表面のうち前記配線層(12)と接している領域の表面粗さRaが1.0μm以下である。好ましくは、主表面のうち前記配線層(12)と接している領域の表面粗さRaが0.3μm以下である。好ましくは、コア基板(1)を備え、前記樹脂絶縁層(2)は前記コア基板(1)の表面を覆うように配置されている。
Also published as
EP6715186
Latest bibliographic data on file with the International Bureau