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Machine translation
1. (WO2006090128) LOGIC CELL LAYOUT ARCHITECTURE WITH SHARED BOUNDARY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2006/090128    International Application No.:    PCT/GB2006/000593
Publication Date: 31.08.2006 International Filing Date: 17.02.2006
IPC:
G06F 17/50 (2006.01)
Applicants: ICERA, INC [US/GB]; 2520 The Quadrant, Aztec West, Almondsbury, Bristol BS32 4AQ (GB) (For All Designated States Except US).
MORTON, Shannon, Vance [AU/GB]; (GB) (For US Only)
Inventors: MORTON, Shannon, Vance; (GB)
Agent: HILL, Justin, John; McDermott Will & Emery UK LLP, 7 Bishopsgate, London EC2N 3AR (GB)
Priority Data:
11/066,712 24.02.2005 US
Title (EN) LOGIC CELL LAYOUT ARCHITECTURE WITH SHARED BOUNDARY
(FR) ARCHITECTURE DE DISPOSITION DE CELLULES LOGIQUES A LIMITE PARTAGEE
Abstract: front page image
(EN)Logic cell layout architecture having a shared boundary between at least two cells each forming logic functions, and a method (200) for designing a logic cell library having a shared boundary between at least two cells (12, 32) is disclosed for increasing packing density and limiting the occurrence of stress between active areas and shallow trench isolation (STI) regions of logic cells within a standard cell library for semiconductor integrated circuits (IC).
(FR)L'invention concerne une architecture de disposition de cellules logiques possédant une limite partagée entre au moins deux cellules formant individuellement des fonctions logiques et un procédé (200) permettant de concevoir une bibliothèque de cellules logiques possédant une limite partagée entre au moins deux cellules (12, 32), aux fins d'augmentation de la densité d'emballage et de limitation de l'apparition de tension entre des zones actives et des régions d'isolation de tranchées peu profondes (STI) des cellules logiques dans une bibliothèque de cellules normalisée destinée à des circuits intégrés semi-conducteurs (IC) .
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)