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Machine translation
1. (WO2006090124) METHOD FOR OPTIMIZING TRANSISTOR PERFORMANCE IN INTEGRATED CIRCUITS BY DIFFUSION SHARING ACROSS CELL BOUNDARIES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2006/090124    International Application No.:    PCT/GB2006/000568
Publication Date: 31.08.2006 International Filing Date: 17.02.2006
IPC:
G06F 17/50 (2006.01), H01L 27/118 (2006.01), H01L 27/02 (2006.01)
Applicants: ICERA, INC. [US/GB]; 2520 The Quadrant, Aztec West, Almondsbury, Bristol BS32 4AQ (GB) (For All Designated States Except US).
HUGHES, Peter, William [GB/GB]; (GB) (For US Only).
MORTON, Shannon, Vance [AU/GB]; (GB) (For US Only).
MONK, Trevor, Kenneth [GB/GB]; (GB) (For US Only)
Inventors: HUGHES, Peter, William; (GB).
MORTON, Shannon, Vance; (GB).
MONK, Trevor, Kenneth; (GB)
Agent: HILL, Justin, John; McDermont Will & Emery UK LLP, 7 Bishopsgate, London EC2N 3AR (GB)
Priority Data:
11/067,200 24.02.2005 US
Title (EN) METHOD FOR OPTIMIZING TRANSISTOR PERFORMANCE IN INTEGRATED CIRCUITS BY DIFFUSION SHARING ACROSS CELL BOUNDARIES
(FR) PROCEDE D'OPTIMISATION DES PERFORMANCES D'UN TRANSISTOR DANS DES CIRCUITS INTEGRES
Abstract: front page image
(EN)A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12) , or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.
(FR)L'invention concerne un procédé (300) permettant d'optimiser les performances d'un transistor dans des circuits intégrés à semi-conducteur construits à partir de cellules standard (12), ou d'une disposition de niveau de transistor sur mesure. Une zone active de diffusion NMOS est étendue avec une zone de liaison (102) entre deux cellules contiguës (112) présentant le même réseau sur la diffusion au niveau des bords contigus de chaque cellule. La zone de diffusion est étendue pour limiter la survenue d'interface active et inactive de manière à minimiser les effets de contrainte de maillage et améliorer les performances du transistor.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)