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Machine translation
1. (WO2006088619) SRAM COMPRISING TFTS AND METHOD OF MANUFACTURING THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2006/088619    International Application No.:    PCT/US2006/002726
Publication Date: 24.08.2006 International Filing Date: 25.01.2006
IPC:
H01L 27/11 (2006.01)
Applicants: ALTERA CORPORATION [US/US]; 101 Innovation Drive, San Jose, California 95134 (US) (For All Designated States Except US).
O, Hugh Sungki [US/US]; (US) (For US Only).
SHIH, Chih-Ching [US/US]; (US) (For US Only).
HUANG, Cheng-Hsiung [US/US]; (US) (For US Only).
LIU, Yow-Juang Bill [US/US]; (US) (For US Only)
Inventors: O, Hugh Sungki; (US).
SHIH, Chih-Ching; (US).
HUANG, Cheng-Hsiung; (US).
LIU, Yow-Juang Bill; (US)
Agent: JACKSON, Robert R.; Fish & Neave IP Group, Ropes & Gray LLP, 1211 Avenue of The Americas, New York, New York 10036-8704 (US)
Priority Data:
11/059,280 16.02.2005 US
Title (EN) SRAM COMPRISING TFTS AND METHOD OF MANUFACTURING THEREOF
(FR) RAM STATIQUE COMPRENANT DES TRANSISTORS EN COUCHES MINCES (TFT) ET PROCEDE DE FABRICATION ASSOCIE
Abstract: front page image
(EN)Methods and apparatus are provided for decreasing soft errors and cell leakage in integrated circuit structures. The structures of the invention preferably include memory cells that utilize thin-film transistors ('TFTs') for the pull-up and pull-down transistors, and well as for the pass-gates. These TFTs preferably include features such as ion implants and a dielectric with a high dielectric constant 'K.' In addition to reducing soft errors and cell leakage, the invention preferably provides other benefits such as low cell area and scalability.
(FR)L'invention concerne des procédés et un appareil permettant de diminuer des erreurs intermittentes et une fuite de cellule dans des structures de circuits intégrés. Lesdites structures comprennent, de préférence, des cellules de mémoire qui utilisent des transistors en couches minces (TFT) pour des transistors d'excursion haute et d'excursion basse, ainsi que pour les grilles de passage. Ces transistors en couches minces (TFT) comportent, de préférence, des caractéristiques, telles que des implants ioniques et un dispositif diélectrique doté d'une constante 'K' diélectrique élevée. En plus de la diminution d'erreurs intermittentes et de fuite de cellule, cette invention a pour objet d'autres avantages, comme une zone cellulaire basse et une variabilité dimensionnelle.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)