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Machine translation
1. (WO2006081057) SIMULTANEOUS PIPELINED READ WITH DUAL LEVEL CACHE FOR IMPROVED SYSTEM PERFORMANCE USING FLASH TECHNOLOGY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2006/081057    International Application No.:    PCT/US2006/000564
Publication Date: 03.08.2006 International Filing Date: 09.01.2006
Chapter 2 Demand Filed:    20.11.2006    
IPC:
G06F 13/00 (2006.01), G06F 12/00 (2006.01)
Applicants: ATMEL CORPORATION [US/US]; 2325 Orchard Parkway, San Jose, California 95131 (US) (For All Designated States Except US)
Inventors: ADUSUMILLI, Vijaya, P.; (US)
Agent: SCHNECK, Thomas; Schneck & Schneck, P.O. Box 2-E, San Jose, California 95109-0005 (US)
Priority Data:
11/043,277 25.01.2005 US
Title (EN) SIMULTANEOUS PIPELINED READ WITH DUAL LEVEL CACHE FOR IMPROVED SYSTEM PERFORMANCE USING FLASH TECHNOLOGY
(FR) LECTURE PIPELINE SIMULTANEE AVEC MEMOIRE CACHE NIVEAU DOUBLE POUR PERFORMANCES DU SYSTEME AMELIOREES UTILISANT LA TECHNOLOGIE FLASH
Abstract: front page image
(EN)A read command protocol (400) and a method of accessing a nonvolatile memory device (100) having an internal cache memory (30-32). A memory device is configured to accept a first and second read command (402, 412), outputting a first requested data (408) from L2 cache (36) through an I/O circuit (40), while simultaneously reading a second requested data (418) from a memory array (10) through a data register (20) into an L1 cache (31). In addition, the memory device may be configured to send or receive a confirmation indicator (406, 416) .
(FR)Protocole de commande de lecture (400) et procédé d'accès à un dispositif de mémoire rémanente (100) ayant une mémoire cache interne (30-32). Un dispositif de mémoire est configuré pour accepter des première et seconde commandes de lecture (402, 412), émettre un premier ensemble de données requises (408) à partir du cache L2 (36) au moyen d'un circuit E/S (40), tout en lisant simultanément un second ensemble de données requises (418) provenant d'un réseau de mémoire (10) au moyen d'un registre de données (20) dans un cache L1 (31). Par ailleurs, le dispositif de mémoire peut être configuré pour envoyer ou recevoir un indicateur de confirmation (406, 416).
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)