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Machine translation
1. (WO2006080062) SWITCH CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2006/080062    International Application No.:    PCT/JP2005/001081
Publication Date: 03.08.2006 International Filing Date: 27.01.2005
IPC:
H01H 9/54 (2006.01), H01H 59/00 (2006.01)
Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA [JP/JP]; 7-3, Marunouchi 2-chome Chiyoda-ku, Tokyo 1008310 (JP) (For All Designated States Except US).
HANGAI, Masatake [JP/JP]; (JP) (For US Only).
NISHINO, Tamotsu [JP/JP]; (JP) (For US Only).
SODA, Shinnosuke [JP/JP]; (JP) (For US Only).
MIYAGUCHI, Kenichi [JP/JP]; (JP) (For US Only).
KAWAKAMI, Kenji [JP/JP]; (JP) (For US Only).
TSURU, Masaomi [JP/JP]; (JP) (For US Only).
HAMANO, Satoshi [JP/JP]; (JP) (For US Only).
MIYAZAKI, Moriyasu [JP/JP]; (JP) (For US Only).
TAKAGI, Tadashi [JP/JP]; (JP) (For US Only)
Inventors: HANGAI, Masatake; (JP).
NISHINO, Tamotsu; (JP).
SODA, Shinnosuke; (JP).
MIYAGUCHI, Kenichi; (JP).
KAWAKAMI, Kenji; (JP).
TSURU, Masaomi; (JP).
HAMANO, Satoshi; (JP).
MIYAZAKI, Moriyasu; (JP).
TAKAGI, Tadashi; (JP)
Agent: SOGA, Michiteru; S. Soga & Co. 8th Floor, Kokusai Building 1-1, Marunouchi 3-chome Chiyoda-ku, Tokyo 1000005 (JP)
Priority Data:
Title (EN) SWITCH CIRCUIT
(FR) CIRCUIT DE COMMUTATION
(JA) スイッチ回路
Abstract: front page image
(EN)A switch circuit comprising a first input/output terminal; a first inductor connected to the first input/output terminal; a capacitor connected to the first inductor; a second input/output terminal connected to the capacitor; a first MEMS switch connected to one end of the capacitor; a second MEMS switch connected to the other end of the capacitor; and a second inductor connected between the first and second MEMS switches; wherein the switch circuit satisfies a relationship of f = 1/(2&pgr;√CL1) = 1/(2&pgr;√CL2), where L1 is the inductance of the first inductor, L2 is the inductance of the second inductor, C is the capacitance of the capacitor, and f is a frequency as used.
(FR)Circuit de commutation comprenant une première borne d'entrée/sortie ; un première bobine d'inductance connectée à la première borne d'entrée/sortie ; un condensateur connecté à la première bobine d'inductance ; une seconde borne d'entrée/sortie connectée au condensateur ; un premier commutateur MEMS connecté à une extrémité du condensateur ; un second commutateur MEMS connecté à l'autre extrémité du condensateur ; et une seconde bobine d'inductance connectée entre le premier et le second commutateur MEMS ; le circuit de commutation satisfaisant à la relation de f = 1/(2pvCL1) = 1/(2pvCL2), où L1 est l'inductance du première bobine d'inductance, L2 est l'inductance de la seconde bobine d'inductance, C est la capacité du condensateur, et f est la fréquence utilisée.
(JA) この発明に係るスイッチ回路は、第1の入出力端子と、前記第1の入出力端子に接続された第1のインダクタと、前記第1のインダクタに接続されたキャパシタと、前記キャパシタに接続された第2の入出力端子と、前記キャパシタの一端に接続された第1のMEMSスイッチと、前記キャパシタの他端に接続された第2のMEMSスイッチと、前記第1のMEMSスイッチ及び前記第2のMEMSスイッチの間に接続された第2のインダクタとを設け、前記第1のインダクタのインダクタンスをL1、前記第2のインダクタのインダクタンスをL2、前記キャパシタのキャパシタンスをC、使用周波数をfとすると、f=1/(2π√CL1)=1/(2π√CL2)の関係を満たす。
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)