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1. WO2006055717 - ROBUST AND HIGH-SPEED MEMORY ACCESS WITH ADAPTIVE INTERFACE TIMING

Publication Number WO/2006/055717
Publication Date 26.05.2006
International Application No. PCT/US2005/041692
International Filing Date 16.11.2005
IPC
G11C 7/10 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G06F 11/1068
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1068in sector programmable memories, e.g. flash disk
G06F 9/4403
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
4401Bootstrapping
4403Processor initialisation
G06F 9/44505
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
445Program loading or initiating
44505Configuring for program initiating, e.g. using registry, configuration files
G11C 16/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
G11C 16/0483
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0483comprising cells having several storage transistors connected in series
G11C 16/26
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
26Sensing or reading circuits; Data output circuits
Applicants
  • QUALCOMM INCORPORATED [US]/[US] (AllExceptUS)
  • CHUN, Dexter Tamio [US]/[US] (UsOnly)
  • PATIL, Ajit [IN]/[US] (UsOnly)
  • HUANG, Ian [CA]/[US] (UsOnly)
  • CHAN, Jason [CA]/[US] (UsOnly)
  • GOLD, Timothy [US]/[US] (UsOnly)
Inventors
  • CHUN, Dexter Tamio
  • PATIL, Ajit
  • HUANG, Ian
  • CHAN, Jason
  • GOLD, Timothy
Agents
  • WADSWORTH, Philip R.
Priority Data
10/993,03418.11.2004US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) ROBUST AND HIGH-SPEED MEMORY ACCESS WITH ADAPTIVE INTERFACE TIMING
(FR) ACCES MEMOIRE ROBUSTE ET A GRANDE VITESSE AVEC SYNCHRONISATION D'INTERFACE ADAPTATIVE
Abstract
(EN) Techniques for quickly and reliably accessing a memory device (e.g., a NAND Flash memory) with adaptive interface timing are described. For memory access with adaptive interface timing, the NAND Flash memory is accessed at an initial memory access rate, which may be the rate predicted to achieve reliable memory access. Error correction coding (ECC), which is often employed for NAND Flash memory, is then used to ensure reliable access of the NAND Flash. For a read operation, one page of data is read at a time from the NAND Flash memory, and the ECC determines whether the page read from the NAND Flash memory contains any errors. If errors are encountered, then a slower memory access rate is selected, and the page with error is read again from the NAND Flash memory at the new rate. The techniques may be used to write data to the NAND Flash memory.
(FR) L'invention concerne des techniques permettant d'accéder rapidement et de manière fiable à une mémoire (par exemple, une mémoire flash NON-ET) avec synchronisation d'interface adaptative. Pour l'accès mémoire avec synchronisation d'interface adaptative, l'accès à la mémoire flash NON-ET a lieu à une vitesse d'accès mémoire initiale, qui peut être la vitesse prédite afin d'obtenir un accès mémoire fiable. Un codage de correction d'erreurs (ECC), qui est souvent utilisé pour une mémoire flash NON-ET, est ensuite utilisé afin d'assurer un accès fiable à la mémoire flash NON-ET. Pour une opération de lecture, une page de données est lue à la fois à partir de la mémoire flash NON-ET et l'ECC détermine si la page lue à partir de la mémoire flash NON-ET contient une quelconque erreur. Si des erreurs sont trouvées, alors une vitesse d'accès mémoire plus lente est sélectionnée et la page présentant l'erreur est lue à nouveau à partir de la mémoire flash NON-ET à la nouvelle vitesse. Lesdites techniques peuvent être utilisées pour écrire des données dans la mémoire flash NON-ET.
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