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1. (WO2006052616) STACKED PACKAGING IMPROVEMENTS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2006/052616 International Application No.: PCT/US2005/039716
Publication Date: 18.05.2006 International Filing Date: 03.11.2005
IPC:
H01L 23/498 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants:
HABA, Belgacem [US/US]; US (UsOnly)
MITCHELL, Craig, S. [US/US]; US (UsOnly)
BEROZ, Masud [US/US]; US (UsOnly)
TESSERA, INC. [US/US]; 3099 Orchard Drive San Jose, California 95134, US (AllExceptUS)
Inventors:
HABA, Belgacem; US
MITCHELL, Craig, S.; US
BEROZ, Masud; US
Agent:
MILLET, Marcus, J. ; Lerner, David, Littenberg, Krumholz & Mentlik, LLP 600 South Avenue West Westfield, New Jersey 07090, US
Priority Data:
60/624,66703.11.2004US
Title (EN) STACKED PACKAGING IMPROVEMENTS
(FR) AMELIORATIONS APPORTEES A DES EMBALLAGES EMPILES
Abstract:
(EN) A plurality of microelectronic assemblies (60) are made by severing an in-process unit including an upper substrate (40) and lower substrate (20) with microelectronic elements (36) disposed between the substrates. In a further embodiment, a lead frame (452) is joined to a substrate (440) so that the leads project from this substrate. Lead frame (452) is joined to a further substrate (470) with one or more microelectronic elements (436, 404, 406) disposed between the substrates.
(FR) L'invention concerne une pluralité d'ensembles microélectroniques (60) formés par séparation d'une unité de traitement comprenant un substrat supérieur (40) et un substrat inférieur (20) entre lesquels sont disposés des éléments microélectroniques (36). Dans un autre mode de réalisation de l'invention, une grille de connexion (452) est assemblée à un substrat (440) de façon que les conducteurs dépassent dudit substrat. La grille de connexion (452) est assemblée à un autre substrat (470) qui comprend un ou plusieurs éléments microélectroniques (436, 404, 406) disposés entre les substrats.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, LY, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)