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1. WO2006035787 - SEMICONDUCTOR DEVICE

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Publication Number WO/2006/035787
Publication Date 06.04.2006
International Application No. PCT/JP2005/017779
International Filing Date 27.09.2005
IPC
H01L 21/822 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
H01L 27/04 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
H01L 21/82 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
CPC
H01L 27/0203
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
0203Particular design considerations for integrated circuits
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applicants
  • 株式会社 東芝 KABUSHIKI KAISHA TOSHIBA [JP]/[JP] (AllExceptUS)
  • 村越 有 MURAKOSHI, Tamotsu [JP]/[JP] (UsOnly)
Inventors
  • 村越 有 MURAKOSHI, Tamotsu
Agents
  • 鈴江 武彦 SUZUYE, Takehiko
Priority Data
2004-28275928.09.2004JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF A SEMICONDUCTEUR
(JA) 半導体装置
front page image
Abstract
(EN)
A semiconductor device is provided with a first power supply line (21) extending in a first direction along one side of a semiconductor chip (11); a first pad row (25) arranged in the first direction adjacent to the first power supply line; a second power supply line (22) extending in the first direction along the first pad row to sandwich the first pad row with the first power supply line; a first buffer circuit (32-2) arranged between the pads in the first pad row to operate by a voltage between the first and the second power supply lines; a second pad row (26) arranged in the first direction adjacent to the second power supply line; a third power supply line (23) extending along the second pad row to sandwich the second pad row with the second power supply line; and a second buffer circuit (31-1) arranged between the pads in the second pad row to operate by a voltage between the second and the third power supply lines.
(FR)
L’invention concerne un dispositif à semiconducteur doté d’une première ligne d’alimentation (21) se prolongeant dans une première direction le long d’un côté d’une puce de semiconducteur (11) ; une première rangée de pastilles (25) disposée dans la première direction en position adjacente à la première ligne d’alimentation ; une deuxième ligne d’alimentation (22) se prolongeant dans la première direction le long de la première rangée de pastilles pour prendre la première rangée de pastilles en sandwich avec la première ligne d’alimentation ; un premier circuit tampon (32-2) disposé entre les pastilles dans la première rangée de pastilles pour fonctionner par une tension entre les première et deuxième lignes d’alimentation ; une deuxième rangée de pastilles (26) disposée dans la première direction en position adjacente à la deuxième ligne d’alimentation ; une troisième ligne d’alimentation (23) se prolongeant le long de la deuxième rangée de pastilles pour prendre la deuxième rangée de pastilles en sandwich avec la deuxième ligne d’alimentation ; et un deuxième circuit tampon (31-1) disposé entre les pastilles dans la deuxième rangée de pastilles pour fonctionner par une tension entre les deuxième et troisième lignes d’alimentation.
(JA)
半導体装置は、半導体チップ（１１）の一辺に沿って第１方向に延設された第１電源線（２１）と、前記第１電源線に隣接し前記第１方向に配列された第１パッド列（２５）と、前記第１パッド列に沿って前記第１電源線との間に前記第１パッド列を挟むように前記第１方向に延設された第２電源線（２２）と、前記第１パッド列におけるパッド間に配置され前記第１、第２電源線間の電圧で動作する第１バッファ回路（３２－２）と、前記第２電源線に隣接して前記第１方向に配列された第２パッド列（２６）と、前記第２パッド列に沿って前記第２電源線との間に前記第２パッド列を挟むように延設された第３電源線（２３）と、前記第２パッド列におけるパッド間に配置され前記第２、第３電源線間の電圧で動作する第２バッファ回路（３１－１）とを具備する。
Also published as
JP2006100436
US20060289897
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