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1. (WO2006026699) METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2006/026699 International Application No.: PCT/US2005/031094
Publication Date: 09.03.2006 International Filing Date: 26.08.2005
IPC:
H01L 21/033 (2006.01) ,H01L 21/308 (2006.01) ,H01L 21/311 (2006.01) ,H01L 21/3213 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
033
comprising inorganic layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
308
using masks
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way P.O. Box 6 Boise, ID 83707-0006, US (AE, AG, AL, AM, AT, AU, AZ, BA, BB, BE, BF, BG, BJ, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GW, HR, HU, ID, IE, IL, IN, IS, IT, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MC, MD, MG, MK, ML, MN, MR, MW, MX, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SI, SK, SL, SM, SN, SY, SZ, TD, TG, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, YU, ZA, ZM, ZW)
ABATCHEV, Mirzafer, K. [RU/US]; US (UsOnly)
SANDHU, Gurtej [GB/US]; US (UsOnly)
TRAN, Luan [US/US]; US (UsOnly)
RERICHA, William, T. [US/US]; US (UsOnly)
DURCAN, Mark, D. [US/US]; US (UsOnly)
Inventors:
ABATCHEV, Mirzafer, K.; US
SANDHU, Gurtej; US
TRAN, Luan; US
RERICHA, William, T.; US
DURCAN, Mark, D.; US
Agent:
HART, Daniel; Knobbe, Martens, Olson & Bear, LLP 2040 Main Street 14th Floor Irvine, CA 92614, US
Priority Data:
10/934,77802.09.2004US
Title (EN) METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION
(FR) METHODE POUR FABRIQUER DES CIRCUITS INTEGRES AU MOYEN D'UNE MULTIPLICATION DE PAS
Abstract:
(EN) A mixed pattern, combining two separately formed patterns (177, 230), is formed on a single mask layer (160) and then transferred to the underlying substrate (110). The first of the separately formed patterns, (177), is formed by pitch multiplication and the second of the separately formed patterns, (230), is formed by conventional photolithography. The first of the separately formed patterns, (177), includes features (175) that are below the resolution of the photolithographic process used to form the second of the separately formed patterns, (230). A protective material (200) is deposited around the spacers (175). The spacers (175) are further protected using a hard mask (210) and then photoresist (220) is formed and patterned over the hard mask (210). The photoresist pattern (230) is transferred through the hard mask (210) to the protective material (200). The combination of the patterns (177 and 230) made out by the spacers (175) and the protective material (200) is then transferred to an underlying amorphous carbon hard mask layer (160). The combined pattern, having features of difference sizes, is then transferred to the underlying substrate (110).
(FR) Dans une étape unique de l'invention, on forme un motif présentant des caractéristiques de tailles différentes sur l'agencement (102) et sur la périphérie (104) d'un circuit intégré (100) d'un substrat (110). En particulier, on forme un motif mélangé, combinant deux motifs formés séparément (177, 230) sur une couche de masque unique (160), puis on le transfère sur le substrat sous-jacent (110). Le premier motif séparément formé (177) est formé par la multiplication de pas, et le second motif séparément formé (230) est formé par une photolytographie classique. Le premier motif (177) comprend des caractéristiques (175) inférieures à celles de la résolution du procédé lithographique utilisé pour former le second motif (230). Ces lignes sont constituées par la formation d'un motif sur du photorésist, puis par l'attaque de ce motif en une couche de carbone amorphe. Des caractéristiques de pas latérales (175) présentant des largeurs inférieures aux largeurs des parties non attaquées du carbone amorphe sont formées sur les parois du carbone amorphe. Le carbone amorphe est ensuite retiré, pour laisser les caractéristiques de pas latérales (175) former le motif de masque (177). Ainsi, les caractéristiques de pas (175) forment le masque (177), ce masque présentant des tailles de caractéristiques inférieures à celles de la résolution du procédé lithographique utilisé pour former le motif sur le photorésist. Une matière de protection (200) est déposée autour des caractéristiques de pas (175). Les caractéristiques de pas (175) sont également protégées au moyen d'un masque dur (210), puis le photorésist (220) est formé pour créer des motifs sur le masque dur (210). Le motif de photorésist (230) est transféré à travers le masque dur (210) sur la matière de protection (200). La combinaison des motifs (177 et 230) constituée par les caractéristiques de pas (175) et par la matière de protection (200) est ensuite transférée sur une couche de masque dur de carbone amorphe sous-jacente (160). Le motif combiné, présentant des caractéristiques de tailles différentes, est ensuite transféré sur le substrat sous-jacent (110).
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020070058578EP2219207EP1789997JP2008512002CN101044596