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1. (WO2006019870) MEMORY BIT LINE SEGMENT ISOLATION
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2006/019870 International Application No.: PCT/US2005/024932
Publication Date: 23.02.2006 International Filing Date: 24.06.2005
IPC:
G11C 16/04 (2006.01) ,G11C 7/00 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
04
using variable threshold transistors, e.g. FAMOS
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
Applicants: SIBIGTROTH, James M.[US/US]; US (UsOnly)
ESPINOR, George L.[US/US]; US (UsOnly)
MORTON, Bruce L.[US/US]; US (UsOnly)
FREESCALE SEMICONDUCTOR, INC.[US/US]; 6501 William Cannon Drive West Austin, TX 78735, US (AllExceptUS)
Inventors: SIBIGTROTH, James M.; US
ESPINOR, George L.; US
MORTON, Bruce L.; US
Agent: KING, Robert L. ; 7700 W. Parmer Lane MD:PL02 Austin, TX 78729, US
Priority Data:
10/912,82406.08.2004US
Title (EN) MEMORY BIT LINE SEGMENT ISOLATION
(FR) ISOLEMENT DE SEGMENTS D'UNE LIGNE BINAIRE DE MEMOIRE
Abstract:
(EN) A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1 BL0, Seg2 BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being erased. In one example, the isolation circuit (16) electrically couples the segments during a read or program of memory cells located on the second segment (Seg2 BL0). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.
(FR) Une seule matrice mémoire (10) présente un circuit d'isolement permettant d'isoler des segments d'une même ligne binaire (Seg1 BL0, Seg2 BL0) les uns des autres. Le circuit d'isolement (16) permet la lecture de cellules mémoire situées dans un segment (12) d'une matrice à lire tandis que les cellules de mémoire d'un autre segment (14) de la matrice sont en cours d'effacement. Dans un exemple, le circuit d'isolement (16) couple électriquement les segments pendant une lecture ou un programme de cellules mémoire situées sur le second segment (Seg2 BL0). L'accès à des informations de programme stockées dans une seule matrice mémoire est toujours possible tandis qu'une partie de la même matrice est effacée. Une variation dynamique de la taille du segment de ligne binaire isolé se produit lorsque de multiples circuits d'isolement sont utilisés pour créer plus de deux segments de matrice.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)