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1. (WO2006018754) FREQUENCY-DIVISION CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2006/018754 International Application No.: PCT/IB2005/052515
Publication Date: 23.02.2006 International Filing Date: 26.07.2005
IPC:
H03K 23/42 (2006.01) ,H03K 23/48 (2006.01) ,H03K 23/50 (2006.01) ,H03K 23/54 (2006.01) ,H03K 23/58 (2006.01) ,H03K 27/00 (2006.01) ,H03K 29/00 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
40
Gating or clocking signals applied to all stages, i.e. synchronous counters
42
Out-of-phase gating or clocking signals applied to counter stages
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
40
Gating or clocking signals applied to all stages, i.e. synchronous counters
48
with a base or radix other than a power of two
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
40
Gating or clocking signals applied to all stages, i.e. synchronous counters
50
using bi-stable regenerative trigger circuits
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
40
Gating or clocking signals applied to all stages, i.e. synchronous counters
50
using bi-stable regenerative trigger circuits
54
Ring counters, i.e. feedback shift register counters
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
58
Gating or clocking signals not applied to all stages, i.e. asynchronous counters
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
27
Pulse counters in which pulses are continuously circulated in a closed loop; Analogous frequency dividers
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
29
Pulse counters comprising multi-stable elements, e.g. for ternary scale, for decimal scale; Analogous frequency dividers
Applicants: BREKELMANS, Johannes, H., A.[NL/NL]; NL (UsOnly)
KONINKLIJKE PHILIPS ELECTRONICS N.V.[NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL (AllExceptUS)
Inventors: BREKELMANS, Johannes, H., A.; NL
Agent: WHITE, Andrew; NXP Semiconductors Intellectual Property Department Cross Oak Lane Redhill, Surrey RH1 5HA, GB
Priority Data:
04103912.413.08.2004EP
Title (EN) FREQUENCY-DIVISION CIRCUIT
(FR) CIRCUIT A REPARTITION FREQUENTIELLE
Abstract:
(EN) A frequency-division circuit comprises a pair of multi-state circuits (MSCA, MSCB). Each multi-state circuit can be switched throughout a cycle of states (SA(l), .., SA(N); SB(1), .., SB(N)). One multi-state circuit (MSCA) switches to a next state in response to a rising edge (Er) in an input signal (OS). The other multi-state circuit (MSCB) switches to a next state in response to a falling edge (Ef) in the input signal (OS). Each multi-state circuit (MSCA, MSCB) has at least one state (SA(l), SB(l)) in which the multi-state circuit inhibits the other multi-state circuit (MSCB, MSCA) so as to prevent the other multi-state circuit from switching to the next state.
(FR) L'invention concerne un circuit à répartition fréquentielle comprenant une paire de circuits (MSCA, MSCB) à états multiples. Chaque circuit à états multiples peut être commuté en fonction d'un cycle d'états (SA(l), .., SA(N); SB(1), .., SB(N)). Un circuit (MSCA) à états multiples est commuté d'un état à un autre en réponse à un front montant (Er) d'un signal (OS) d'entrée. L'autre circuit (MSCB) à états multiples est commuté d'un état à un autre en réponse à un front descendant (Ef) du signal (OS) d'entrée. Chaque circuit (MSCA, MSCB) à états multiples comprend au moins un état (SA(l), SB(l)) dans lequel le circuit à états multiples inhibe l'autre circuit (MSCB, MSCA) à états multiples de manière à prévenir la commutation de l'autre circuit à états multiples d'un état à l'autre.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)