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1. (WO2006016611) IRREGULARITIES SIMULATION SYSTEM
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2006/016611 International Application No.: PCT/JP2005/014668
Publication Date: 16.02.2006 International Filing Date: 10.08.2005
IPC:
G06F 19/00 (2006.01) ,G06F 17/50 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
19
Digital computing or data processing equipment or methods, specially adapted for specific applications
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
50
Computer-aided design
Applicants: TAKEUCHI, Kiyoshi[JP/JP]; JP (UsOnly)
NEC CORPORATION[JP/JP]; 7-1, Shiba 5-chome, Minato-ku, Tokyo 1088001, JP (AllExceptUS)
Inventors: TAKEUCHI, Kiyoshi; JP
Agent: KATO, Asamichi; c/o A. Kato & Associates daVinci BOSEI 7th Floor 20-12 Shin-Yokohama 3-chome Kohoku-ku, Yokohama-shi Kanagawa 2220033, JP
Priority Data:
2004-23583113.08.2004JP
2005-18390423.06.2005JP
Title (EN) IRREGULARITIES SIMULATION SYSTEM
(FR) SYSTÈME DE SIMULATION D’IRRÉGULARITÉS
(JA) ばらつきシミュレーション・システム
Abstract:
(EN) There is provided an irregularities simulation system enabling easy circuit design suppressing performance deterioration attributed to irregularities. An irregularities analysis unit (100) extracts in advance statistical characteristic of irregularities from a plenty of device samples. A model analysis unit (200) checks response to the parameter fluctuation of the circuit simulation. A fitting execution unit (300) combines these information and decides the parameter irregularities distribution so that circuit simulation reproduce the statistical characteristic of the device samples.
(FR) Est ici dévoilé un système de simulation d’irrégularités permettant de concevoir facilement un circuit qui supprime la dégradation des performances due aux irrégularités. Une unité d’analyse des irrégularités (100) extrait par avance la caractéristique statistique des irrégularités d’un grand nombre d’échantillons du dispositif. Une unité d’analyse modèle (200) vérifie la réponse à la fluctuation du paramètre de simulation du circuit. Une unité d’exécution d’ajustement (300) combine ces informations et décide de la distribution des irrégularités de paramètre de façon que la simulation du circuit reproduit la caractéristique statistique des échantillons du dispositif.
(JA)  ばらつきによる性能劣化を抑えた回路設計を容易にするばらつきシミュレーション・システムの提供。  ばらつき分析部100は、予め多数のデバイス標本からばらつきの統計的特長を抽出し、モデル分析部200は、回路シミュレーション出力のパラメータ変動に対する応答を調べ、フィッティング実行部300は、これら情報をつき合わせて、回路シミュレーションが、デバイス標本の統計的特長を再現するようにパラメータのばらつき方を決定する。
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)