Processing

Please wait...

Settings

Settings

Goto Application

1. WO2006016299 - INTEGRATED F-CLASS AMPLIFIER WITH OUTPUT PARASITIC CAPACITANCE COMPENSATION

Publication Number WO/2006/016299
Publication Date 16.02.2006
International Application No. PCT/IB2005/052484
International Filing Date 25.07.2005
IPC
H03F 1/14 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
1Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
08Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
14by use of neutralising means
H03F 1/08 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
1Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
08Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
H03F 3/191 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
3Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
189High-frequency amplifiers, e.g. radio frequency amplifiers
19with semiconductor devices only
191Tuned amplifiers
H03F 3/217 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
3Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
21with semiconductor devices only
217Class D power amplifiers; Switching amplifiers
CPC
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/4813
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
4813Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
H01L 27/0207
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
0203Particular design considerations for integrated circuits
0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
H01L 2924/1305
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
10Details of semiconductor or other solid state devices to be connected
11Device type
13Discrete devices, e.g. 3 terminal devices
1304Transistor
1305Bipolar Junction Transistor [BJT]
H01L 2924/13091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
10Details of semiconductor or other solid state devices to be connected
11Device type
13Discrete devices, e.g. 3 terminal devices
1304Transistor
1306Field-effect transistor [FET]
13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
H01L 2924/30107
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
30Technical effects
301Electrical effects
30107Inductance
Applicants
  • KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL]/[NL] (AllExceptUS)
  • BLEDNOV, Igor [RU]/[NL] (UsOnly)
Inventors
  • BLEDNOV, Igor
Agents
  • ELEVELD, Koop, J.
Priority Data
04103835.709.08.2004EP
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) INTEGRATED F-CLASS AMPLIFIER WITH OUTPUT PARASITIC CAPACITANCE COMPENSATION
(FR) AMPLIFICATEUR INTEGRE DE CLASSE F A COMPENSATION DE CAPACITE DE SORTIE PARASITE
Abstract
(EN) The present invention relates to an integrated F-class amplifier arrangement with a semiconductor power device (100) for receiving a first signal (In) and for amplifying the first signal (In) to generate a first amplified signal. Said F-class amplifier stage (100) comprises an output compensation circuit (OCC) for compensating a parasitic output capacitance of the at least first amplifier stage at fundamental frequency and at least one odd or even multiple thereof.
(FR) L'invention concerne un agencement d'amplificateur intégré de classe F comprenant un dispositif de puissance (100) semi-conducteur, destiné à recevoir un premier signal (In) et à amplifier ce premier signal (In) afin de générer un premier signal amplifié. Un étage d'amplificateur (100) de classe F comprend un circuit de compensation de sortie (OCC) permettant de compenser une capacité de sortie parasite du premier étage d'amplificateur à une fréquence fondamentale et au moins un multiple pair ou impair de celle-ci.
Latest bibliographic data on file with the International Bureau