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Machine translation
1. (WO2006013658) FLAT DISPLAY AND ITS DRIVING METHOD
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2006/013658    International Application No.:    PCT/JP2005/007044
Publication Date: 09.02.2006 International Filing Date: 11.04.2005
IPC:
G09G 3/28 (2006.01), G09G 3/20 (2006.01)
Applicants: FUJITSU HITACHI PLASMA DISPLAY LIMITED [JP/JP]; 1815, Tajiri, Kunitomi-cho, Higashimorokata-gun Miyazaki, 880-1194 (JP) (For All Designated States Except US).
KAWADA, Toyoshi [JP/JP]; (JP) (For US Only).
ISHIDA, Katsuhiro [JP/JP]; (JP) (For US Only).
SANO, Yuji [JP/JP]; (JP) (For US Only).
OKADA, Yoshinori [JP/JP]; (JP) (For US Only)
Inventors: KAWADA, Toyoshi; (JP).
ISHIDA, Katsuhiro; (JP).
SANO, Yuji; (JP).
OKADA, Yoshinori; (JP)
Agent: AOKI, Atsushi; SEIWA PATENT & LAW Toranomon 37 Mori Bldg. 5-1, Toranomon 3-chome Minato-ku, Tokyo 105-8423 (JP)
Priority Data:
2004-229474 05.08.2004 JP
Title (EN) FLAT DISPLAY AND ITS DRIVING METHOD
(FR) AFFICHAGE PLAT ET SON PROCEDE D’ATTAQUE
(JA) フラットディスプレイ装置およびその駆動方法
Abstract: front page image
(EN)A flat display comprises a flat display panel in which at least a part of display electrodes are composed of a scan electrode and address electrodes crossing each other. The flat display has a characteristic that when the drive load of the flat display panel becomes large, the activation energy of the discharge gas becomes high and the drive voltage becomes low. By a method of driving the flat display, when the drive load of the flat display panel becomes large (S1 to S4), the drive voltage of the scan electrode or the drive voltage (Vd) of the address electrode is reduced.
(FR)L’invention concerne un affichage plat comprenant un panneau d’affichage plat dans lequel au moins une partie des électrodes d’affichage comprend une électrode de balayage et des électrodes d’adressage qui se croisent. L’affichage plat est caractérisé en ce que, lorsque la charge d’attaque du panneau d’affichage plat augmente, l’énergie d’activation du gaz de décharge augmente et la tension d’attaque diminue. L’invention concerne également un procédé d’attaque de l’affichage plat permettant de réduire la tension d’attaque de l’électrode de balayage ou la tension d’attaque (Vd) des électrodes d’adressage lorsque la charge d’attaque du panneau d’affichage plat augmente (S1 à S4).
(JA) フラットディスプレイ装置は、互いに交差する走査電極およびアドレス電極により少なくとも表示電極の一部が構成されたフラットディスプレイパネルを備え、該フラットディスプレイパネルの駆動負荷量が大きくなると放電ガスの活性化エネルギーが高くなって駆動電圧が低くなる特性を有する。このフラットディスプレイ装置の駆動方法は、前記フラットディスプレイパネルの駆動負荷量が大きくなると(S1~S4)、前記走査電極の駆動電圧または前記アドレス電極の駆動電圧(Vd)を低下させる。
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)