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1. (WO2005124293) METHOD OF FORMING A SEMICONDUCTOR LAYER USING A PHOTOMASK RETICLE HAVING MULTIPLE VERSIONS OF THE SAME MASK PATTERN WITH DIFFERENT BIASES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2005/124293    International Application No.:    PCT/US2005/020424
Publication Date: 29.12.2005 International Filing Date: 09.06.2005
Chapter 2 Demand Filed:    12.04.2006    
IPC:
G01F 9/00 (2006.01), G03C 5/00 (2006.01), G06F 17/50 (2006.01)
Applicants: PHOTRONICS, INC. [US/US]; 15 Secor Road, P.O. box 5226, Brookfield, Connecticut 06804 (US) (For All Designated States Except US).
ROCKWELL, Barry, K. [US/US]; (US) (For US Only).
TRACY, Jeffrey, W. [US/US]; (US) (For US Only).
VOKOUN, Edward [US/US]; (US) (For US Only)
Inventors: ROCKWELL, Barry, K.; (US).
TRACY, Jeffrey, W.; (US).
VOKOUN, Edward; (US)
Agent: LO CICERO, Anthony, F.; Amster, Rothstein & Ebenstein LLP, 90 Park Avenue, New York, NY 10016 (US)
Priority Data:
10/866,976 14.06.2004 US
10/920,475 18.08.2004 US
Title (EN) METHOD OF FORMING A SEMICONDUCTOR LAYER USING A PHOTOMASK RETICLE HAVING MULTIPLE VERSIONS OF THE SAME MASK PATTERN WITH DIFFERENT BIASES
(FR) PROCEDE DE FORMATION D'UNE COUCHE DE SEMI-CONDUCTEUR AU MOYEN D'UN RETICULE DE PHOTOMASQUES COMPORTANT PLUSIEURS VERSIONS DU MEME DESSIN DE MASQUE POUR DIFFERENTES POLARITES
Abstract: front page image
(EN)A method of forming a semiconductor layer of a semiconductor device including interposing a reticle between an energy source and a semiconductor wafer, the reticle including at least two duplicate mask patterns each having a different bias, and passing energy through an opening in a shutter and through one of the at least two duplicate mask patterns using the energy source to form an image on the semiconductor wafer. The one of the at least two duplicate mask patterns is chosen based on a required bias. The at least two duplicate mask patterns are disposed in a side by side relationship to one another and extend parallel or transverse to the shutter opening.
(FR)La présente invention concerne un procédé de formation d'une couche de semi-conducteur pour un dispositif semi-conducteur. A cet effet, on interpose entre une source d'énergie et une plaquette de semi-conducteur un réticule comportant au moins deux dessins de masque en double correspondant à une polarité différente. On fait passer de l'énergie au travers d'un orifice à obturateur et au travers de l'un des deux dessins de masque en double, utilisant la source d'énergie pour former une image sur la plaquette de semi-conducteur. Le choix du dessin se fait en fonction de la polarité demandée. Ces dessins sont disposées côte à côte l'un de l'autre, parallèlement ou transversalement à l'orifice à obturateur.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)