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Machine translation
1. (WO2005119902) IMAGE REMOVING CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2005/119902    International Application No.:    PCT/JP2005/009578
Publication Date: 15.12.2005 International Filing Date: 25.05.2005
IPC:
H03D 7/18 (2006.01), H04B 1/26 (2006.01)
Applicants: NIIGATA SEIMITSU CO., LTD. [JP/JP]; 5-13, Nishishirocho 2-chome Joetsu-shi, Niigata 9430834 (JP) (For All Designated States Except US).
AOYAMA, Takashi [JP/JP]; (JP) (For US Only).
MIYAGI, Hiroshi [JP/JP]; (JP) (For US Only)
Inventors: AOYAMA, Takashi; (JP).
MIYAGI, Hiroshi; (JP)
Agent: OSUGA, Yoshiyuki; 3rd Fl., Nibancho Bldg. 8-20, Nibancho Chiyoda-ku, Tokyo 1020084 (JP)
Priority Data:
2004-165638 03.06.2004 JP
Title (EN) IMAGE REMOVING CIRCUIT
(FR) CIRCUIT D'ELIMINATION D'IMAGE
(JA) イメージ除去回路
Abstract: front page image
(EN)An image removing circuit which can remove an image signal without being affected by element variance generated upon manufacture of elements such as resistance and capacitor. The image removing circuit is composed of a first mixer part (2), which mixes a receiving signal from a receiver with a first local oscillation signal generated by a local oscillation circuit (1); a second mixer part (3), which mixes the receiving signal with a second local oscillation signal provided by shifting the local oscillation signal generated by the local oscillation circuit (1) at 90°; a polyphase filter circuit (4) composed of a capacitor (C1) and a switched capacitor; and a composing/outputting part (5) which composes and outputs an IF signal outputted from the polyphase filter circuit (4).
(FR)Un circuit d'Elimination d'image qui permet d'Eliminer un signal d'image sans Etre affectE par la variance des ElEments produite au moment de la fabrication d'ElEments, tels que des rEsistances et des condensateurs. Le circuit d'Elimination d'image se compose d'une premiEre partie mElangeur (2), qui mElange un signal de rEception provenant d'un rEcepteur avec un premier signal d'oscillation local produit par un circuit d'oscillation local (1); d'une deuxiEme partie mElangeur (3), qui mElange un signal de rEception avec un deuxiEme signal d'oscillation local produit par le décalage du signal d'oscillation local produit par le circuit d'oscillation local (1) A 90 °C; d'un circuit de filtrage polyphasé (4) composE d'un condensateur (C1) et d'un condensateur commutE; et d'une partie de composition/sortie (5) qui compose et produit en sortie un signal FI provenant du circuit de filtrage polyphasé (4).
(JA) 製造時の抵抗やコンデンサ等の素子のバラツキに影響されることなくイメージ信号を除去することが可能なイメージ除去回路を提供するために、受信機からの受信信号と局部発振回路1によって生成された第1の局部発振信号とを混合する第1のミキサ部2と、受信信号と局部発振回路1によって生成された局部発振信号を90°シフトした第2の局部発振信号とを混合する第2のミキサ部3と、コンデンサC1とスイッチトキャパシタによって構成されたポリフェーズフィルタ回路4と、ポリフェーズフィルタ回路4から出力されたIF信号を合成して出力するための合成出力部5とによってイメージ除去回路を構成する。
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)