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1. (WO2005117116) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2005/117116 International Application No.: PCT/JP2005/005690
Publication Date: 08.12.2005 International Filing Date: 28.03.2005
IPC:
H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants: TERAO, Kohtaro[JP/JP]; JP (UsOnly)
Sanken Electric Co., Ltd.[JP/JP]; 6-3, Kitano 3-chome, Niiza-shi, Saitama 3528666, JP (AllExceptUS)
Inventors: TERAO, Kohtaro; JP
Agent: SHIMIZU, Keiichi; Kouwa Patent Office 3rd Floor, YK Nakameguro Building 1-5, Nakameguro 3-chome Meguro-ku, Tokyo 1530061, JP
Priority Data:
2004-16205531.05.2004JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) A multilayer semiconductor device in which heat dissipation properties are enhanced. A coupling lead (4) connected between an MOSFET (1) and a control IC (2) on a supporting plate (3) of the semiconductor device comprises a base body (6) having one end (6a) forming one major surface (4a) of a coupling lead (4) conductively bonded with the other major surface (1b) of the MOSFET (1) and exhibiting heat dissipation properties and conductivity, and a body to be coated (7) bonded onto one end (6a) of the base body (6) and forming the other major surface (4b) of the coupling lead (4) supporting the control IC (2) while exhibiting electric insulation and high heat transmission resistance. A current is supplied to the MOSFET (1) through the supporting plate (3) and the base body (6) of the coupling lead (4) becoming a current passage, and heat generated through operation of the MOSFET (1) is dissipated efficiently through the supporting plate (3) and the base body (6) of the coupling lead (4), thus supplying a large current to the MOSFET (1) while ensuring sufficient heat dissipation properties.
(FR) Il est prévu un dispositif semi-conducteur en plusieurs couches améliorant les propriétés de dissipation thermique. Un fil d’accouplement (4) connecté entre un MOSFET (1) et un CI de commande (2) sur une plaque support (3) du dispositif semi-conducteur comprend un corps de base (6) dont une extrémité (6a) forme une surface importante (4a) d’un fil d’accouplement (4) reliée de manière conductrice à l’autre surface importante (1b) du MOSFET (1) avec des propriétés de dissipation thermique et de conductivité, et un corps à revêtir (7) accroché en une extrémité (6a) du corps de base (6) et formant l’autre surface importante (4b) du fil d’accouplement (4) supportant le CI de commande (2) tout en présentant une isolation électrique et une résistance élevée de transmission thermique. On injecte du courant dans le MOSFET (1) à travers la plaque support (3) et le corps de base (6) du fil d’accouplement (4) devenant un passage de courant, et la chaleur générée par le fonctionnement du MOSFET (1) est dissipée de manière efficace à travers la plaque support (3) et le corps de base (6) du fil d’accouplement (4), injectant ainsi un courant important dans le MOSFET (1) tout en garantissant alors des propriétés suffisantes de dissipation thermique.
(JA)  積層型の半導体装置の放熱性を改善する。半導体装置の支持板(3)上でMOSFET(1)と制御IC(2)との間に接続される連結リード(4)は、MOSFET(1)の他方の主面(1b)に通電可能に固着された連結リード(4)の一方の主面(4a)を形成する一端(6a)を有し且つ放熱性と導電性とを備えた基体(6)と、基体(6)の一端(6a)上に固着され且つ制御IC(2)を支持する連結リード(4)の他方の主面(4b)を形成する電気絶縁性と高伝熱抵抗性の被覆体(7)とを備える。電流通路となる支持板(3)と連結リード(4)の基体(6)とを通じてMOSFET(1)に電流を供給すると共に、MOSFET(1)の動作により発生する熱を支持板(3)と連結リード(4)の基体(6)とを通じて効率よく放出し、十分な放熱性を確保して、MOSFET(1)に大きな電流を流すことができる。
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)