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1. (WO2005114670) PIPELINED DATA RELOCATION AND IMPROVED CHIP ARCHITECTURES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2005/114670 International Application No.: PCT/US2005/016341
Publication Date: 01.12.2005 International Filing Date: 09.05.2005
IPC:
G11C 7/10 (2006.01) ,G11C 16/34 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
10
Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
34
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
Applicants: GOROBETS, Sergey, Anatolievich[RU/GB]; GB (UsOnly)
CONLEY, Kevin, M.[US/US]; US (UsOnly)
SANDISK CORPORATION[US/US]; 601 McCarthy Boulevard Milpitas, CA 95035, US (AE, AG, AL, AM, AT, AU, AZ, BA, BB, BE, BF, BG, BJ, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GW, HR, HU, ID, IE, IL, IN, IS, IT, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MC, MD, MG, MK, ML, MN, MR, MW, MX, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SI, SK, SL, SM, SN, SY, SZ, TD, TG, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, YU, ZA, ZM, ZW)
Inventors: GOROBETS, Sergey, Anatolievich; GB
CONLEY, Kevin, M.; US
Agent: PARSONS, Gerald, P. ; Parsons, Hsue & de Runtz LLP 595 Market Street Suite 1900 San Francisco, CA 94105, US
Priority Data:
10/846,28913.05.2004US
Title (EN) PIPELINED DATA RELOCATION AND IMPROVED CHIP ARCHITECTURES
(FR) TRANSLATION DE DONNEES PIPELINE ET ARCHITECTURES DE PUCES AMELIOREES
Abstract:
(EN) The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.
(FR) L'invention concerne des procédés et des architectures permettant le traitement parallèle d'opération de lecture avec des opérations d'écriture. Plus précisément, l'invention concerne des procédés de traitement parallèle d'opérations de translation de données qui permettent de vérifier et de corriger des données dans le contrôleur avant de les réécrire, mais qui réduisent ou éliminent le retard supplémentaire susceptible de se produire normalement. Un certain nombre d'améliorations architecturales sont décrites qui facilitent ces procédés, notamment l'introduction de deux registres dans la mémoire, auxquels le contrôleur peut accéder de manière indépendante, ce qui permet d'écrire à partir d'un premier registre de mémoire et, parallèlement, d'écrire vers un second registre ; d'introduire deux registres dans la mémoire, les contenus des registres pouvant être permutés.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)