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Machine translation
1. (WO2005114433) INTEGRATED CIRCUIT WITH A PLURALITY OF HOST PROCESSOR FAMILY TYPES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2005/114433    International Application No.:    PCT/US2005/017483
Publication Date: 01.12.2005 International Filing Date: 19.05.2005
IPC:
G06F 3/00 (2006.01), G06F 5/00 (2006.01), G06F 13/00 (2006.01)
Applicants: GALLITZIN ALLEGHENY LLC [US/US]; 171 Main Street, #271, Los Altos, CA 94022 (US) (For All Designated States Except US).
SCHMIDT, Dominik, J. [US/US]; (US) (For US Only)
Inventors: SCHMIDT, Dominik, J.; (US)
Agent: ROZMAN, Mark, J.; Trop, Pruner & Hu, P.C., 8554 Katy Freeway, Ste. 100, Houston, TX 77024 (US)
Priority Data:
10/690,266 20.05.2004 US
Title (EN) INTEGRATED CIRCUIT WITH A PLURALITY OF HOST PROCESSOR FAMILY TYPES
(FR) CIRCUIT INTEGRE COMPRENANT UNE PLURALITE DE TYPES DE FAMILLE DE PROCESSEURS HOTES
Abstract: front page image
(EN)An integrated circuit capable of supporting a plurality of host processor families includes a host processor belonging to a first processor family (Fig. 1, 148); a reconfigurable processor core (Fig. 1, 150) coupled to the host processor, the reconfigurable processor core having a core portion processing instructions belonging to a second host processor family (Fig. 1, 155); and a processor type select circuit to configure the integrated circuit to process instructions belonging to one of the first or second host processor family instruction set.
(FR)L'invention concerne un circuit intégré capable de supporter une pluralité de familles de processeurs hôtes, comprenant un processeur hôte appartenant à une première famille de processeur ; un noyau de processeur reconfigurable couplé au processeur hôte, ce dernier présentant des instructions traitant une partie noyau appartenant à une seconde famille de processeurs hôtes, et un circuit de sélection de type processeur permettant de configurer le circuit intégré aux instructions de traitement appartenant au premier ou au second ensemble d'instructions de famille de processeur hôte.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)