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1. (WO2005104443) PROGRAMMABLE HARDWARE FOR DEEP PACKET FILTERING

Pub. No.:    WO/2005/104443    International Application No.:    PCT/US2005/013629
Publication Date: Nov 3, 2005 International Filing Date: Apr 19, 2005
IPC: G06F 17/00
Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
CHO, Young, H.
MANGIONE-SMITH, William, H.
Inventors: CHO, Young, H.
MANGIONE-SMITH, William, H.
Title: PROGRAMMABLE HARDWARE FOR DEEP PACKET FILTERING
Abstract:
An improved deep packet filter system designed to optimize search of dynamic patterns for a high speed network traffic. The improved deep packet filter system is a hardware-based system with optimized logic area. One optimization technique is the sharing of common sub-logic in the hardware design to reduce the number of gates that are required. Another optimization technique is the use of a built-in memory to store portions of the pattern set, also resulting in a reduction of gates. The reduction of the logic area allows the deep packet filter system to be implemented onto a single field-programmable array chip.