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1. (WO2005104236) OPTICAL DEVICES FEATURING TEXTURED SEMICONDUCTOR LAYERS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2005/104236 International Application No.: PCT/US2005/012849
Publication Date: 03.11.2005 International Filing Date: 15.04.2005
Chapter 2 Demand Filed: 14.02.2006
IPC:
G02F 1/017 (2006.01) ,H01L 21/18 (2006.01) ,H01L 21/20 (2006.01) ,H01L 21/302 (2006.01)
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
015
based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction
017
Structures with periodic or quasi periodic potential variation, e.g. superlattices, quantum wells
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
Applicants:
MOUSTAKAS, Theodore, D. [US/US]; US (UsOnly)
CABALU, Jasper, S. [PH/US]; US (UsOnly)
TRUSTEES OF BOSTON UNIVERSITY [US/US]; One Sherborn Street Boston, MA 02215, US (AllExceptUS)
Inventors:
MOUSTAKAS, Theodore, D.; US
CABALU, Jasper, S.; US
Agent:
GAGNEBIN, Charles, L., III ; Weingarten, Schurgin, Gagnebin & Lebovici, LLP Ten Post Office Square Boston, MA 02109, US
Priority Data:
60/562,48915.04.2004US
60/615,04701.10.2004US
60/645,70421.01.2005US
Title (EN) OPTICAL DEVICES FEATURING TEXTURED SEMICONDUCTOR LAYERS
(FR) DISPOSITIF OPTIQUES COMPORTANT DES COUCHES SEMI-CONDUCTRICES TEXTUREES
Abstract:
(EN) A semiconductor sensor, solar cell or emitter or a precursor therefore having a substrate and textured semiconductor layer deposited onto the substrate. The layer can be textured as grown on the substrate or textured by replicating a textured substrate surface. The substrate or first layer is then a template for growing and texturing other semiconductor layers from the device. The textured layers are replicated to the surface from the substrate to enhance light extraction or light absorption. Multiple quantum wells, comprising several barrier and quantum well layers, are deposited as alternating textured layers. The texturing in the region of the quantum well layers greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. This is the case in nitride semiconductors grown along the polar [0001] or [000-1] directions.
(FR) La présente invention a trait à un capteur, une cellule solaire ou un émetteur à semi-conducteurs ou un précurseur de ceux-ci comportant un substrat et une couche semi-conductrice texturée déposée sur le substrat. La couche peut être texturée telle que produite par croissance sur le substrat ou texturée par la réplication d'une surface de substrat texturée. Le substrat ou première couche constitue alors une matrice pour la croissance et la texturation d'autres couches semi-conductrices à partir du dispositif. Les couches texturées sont produites par réplication à la surface à partir du substrat pour améliorer l'extraction de lumière ou l'absorption de lumière. Une pluralité de puits quantiques, comprenant plusieurs couches barrière et de puits quantiques, sont déposés sous la forme de couches texturées alternées. La texturation dans la région des couches de puits quantiques améliore considérablement l'efficacité quantique si le semi-conducteur est polaire et la croissance des puits quantiques est réalisée selon les directions polaires [0001] ou [000-1]
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)