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1. WO2005066968 - MEMORY SYSTEM SEGEMENTED POWER SUPPLY AND CONTROL

Publication Number WO/2005/066968
Publication Date 21.07.2005
International Application No. PCT/US2004/043496
International Filing Date 22.12.2004
IPC
G11C 5/14 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
14Power supply arrangements
G11C 11/406 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
G11C 11/4074 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
CPC
G11C 11/406
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
G11C 11/4074
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 2207/104
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
10Aspects relating to interfaces of memory device to external buses
104Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
G11C 2211/4067
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2211Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
401Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
406Refreshing of dynamic cells
4067Refresh in standby or low power modes
G11C 5/14
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
14Power supply arrangements
Applicants
  • INTEL CORPORATION [US]/[US] (AllExceptUS)
  • ELLIS, Robert, M. [US]/[US] (UsOnly)
  • MOONEY, Stephen, R. [US]/[US] (UsOnly)
  • KENNEDY, Joseph, T. [US]/[US] (UsOnly)
Inventors
  • ELLIS, Robert, M.
  • MOONEY, Stephen, R.
  • KENNEDY, Joseph, T.
Agents
  • MALLIE, Michael, J.
Priority Data
10/748,46029.12.2003US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY SYSTEM SEGEMENTED POWER SUPPLY AND CONTROL
(FR) ALIMENTATION ET COMMANDE SEGMENTEES DE SYSTEMES DE MEMOIRE
Abstract
(EN)
A memory device having memory cells supplied with a separate higher voltage power than the separate power supplied to memory logic, and a lower power state that entails removing power from at least some of the logic such that refresh operations to preserve the contents of the memory cells continue to take place, but at least some of the interface to the memory device is powered down to reduce power consumption.
(FR)
L'invention concerne un dispositif de mémoire comprenant des cellules de mémoire alimentées en tension séparée supérieure à celle fournie au circuit logique de mémoire, et un état de puissance inférieur impliquant le retrait de puissance d'au moins un circuit logique, de sorte que les opération de rafraîchissement permettant de conserver le contenu des cellules de mémoire continues se poursuivent, mais qu'au moins l'interface vers le dispositif de mémoire soit mise hors tension pour réduire la consommation d'énergie.
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