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1. WO2005065325 - OPTIMIZED CONTACT DESIGN FOR THERMOSONIC BONDING OF FLIP-CHIP DEVICES

Publication Number WO/2005/065325
Publication Date 21.07.2005
International Application No. PCT/US2004/043751
International Filing Date 22.12.2004
IPC
H01L 27/15 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
15including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 29/22 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
12characterised by the materials of which they are formed
22including, apart from doping materials or other impurities, only AIIBVI compounds
CPC
H01L 2224/05568
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
05568the whole external layer protruding from the surface
H01L 2224/05573
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05573Single external layer
H01L 2224/0603
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
0601Structure
0603Bonding areas having different sizes, e.g. different heights or widths
H01L 2224/06102
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
061Disposition
06102the bonding areas being at different heights
H01L 2224/0615
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
061Disposition
0612Layout
0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
H01L 2224/16
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
Applicants
  • GELcore LLC [US]/[US] (AllExceptUS)
Inventors
  • ELIASHEVICH, Ivan
  • VENUGOPALAN, Hari, S.
  • GOA, Xiang
  • SACKRISON, Michael, J.
Agents
  • CORNELY, John, P.
Priority Data
60/532,84024.12.2003US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) OPTIMIZED CONTACT DESIGN FOR THERMOSONIC BONDING OF FLIP-CHIP DEVICES
(FR) MODELE DE CONTACT OPTIMISEE POUR METALLISATION THERMOSONIQUE DE DISPOSITIFS DE CONNEXION PAR BOSSAGES
Abstract
(EN)
A light emitting device (A) includes a semiconductor die (100). The semiconductor die includes: an epitaxial structure (120) arranged on a substrate (160), the epitaxial structure forming an active light generating region (140) between a first layer (120n) on a first side of the active region and having a first conductivity type, and a second layer (120p) on a second side of the active region and having a second conductivity type, the second side of the active region being opposite the first side of the active region and the second conductivity type being different that the first conductivity type; a first contact (180n) in operative electrical communication with the active region via the first layer in the epitaxial structure, the first contact being arranged on a side of the epitaxial structure opposite the substrate; a second contact (180p) in operative electrical communication with the active region via the second layer in the epitaxial structure, the second contact being arranged on a side of the epitaxial structure opposite the substrate; a first contact trace corresponding to the first contact and defined at a surface thereof distal from the substrate, the first trace including at least one area designated for bonding (320n); and, a second contact trace corresponding the second contact and defined at a surface thereof distal from the substrate, the second trace including at least one area (320p) designated for bonding. Suitably, the first contact trace is substantially enclosed within the second contact trace.
(FR)
L'invention concerne un dispositif électroluminescent (A) comprenant un dé semiconducteur (100). Le dé semiconducteur comprend une structure épitaxiale (120) disposée sur un substrat (160) et formant une région active de génération de lumière (140) entre une première couche (120n) située sur un premier côté de la région active et présentant un premier type de conductivité, et une seconde couche (120p) située sur un second côté de la région active et présentant un second type de conductivité, le second côté de la région active étant opposé au premier côté de la région active, et le second type de conductivité étant différent du premier type de conductivité. Le dé semiconducteur comprend également un premier contact (180n) en communication électrique fonctionnelle avec la région active par l'intermédiaire de la première couche ménagée dans la structure épitaxiale, ledit premier contact étant disposé sur un côté de la structure épitaxiale opposé au substrat; un second contact (180p) en communication électrique fonctionnelle avec la région active par l'intermédiaire de la seconde couche ménagée dans la structure épitaxiale, ledit second contact étant disposé sur un côté de la structure épitaxiale opposé au substrat; un premier tracé métallique de contact correspondant au premier contact et délimité au niveau d'une surface de ce dernier distale du substrat, ledit premier tracé métallique comprenant au moins une zone (320n) conçue pour être métallisée; et un second tracé métallique de contact correspondant au second contact et délimité au niveau d'une surface de ce dernier distale du substrat, ledit second tracé métallique comprenant au moins une zone (320p) conçue pour être métallisée. Le premier tracé métallique de contact est judicieusement encapsulé à l'intérieur du second tracé métallique de contact.
Also published as
US2007145379
Latest bibliographic data on file with the International Bureau