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1. WO2005064434 - INTEGRATED CIRCUIT CLOCK DISTRIBUTION

Publication Number WO/2005/064434
Publication Date 14.07.2005
International Application No. PCT/IB2004/004026
International Filing Date 06.12.2004
IPC
G06F 1/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
06Clock generators producing several clock signals
G06F 1/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
10Distribution of clock signals
CPC
G06F 1/06
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
06Clock generators producing several clock signals
G06F 1/10
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
10Distribution of clock signals ; , e.g. skew
Applicants
  • KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL]/[NL] (AllExceptUS)
  • DUVILLARD, Sylvain [FR]/[FR] (UsOnly)
  • DELBAERE, Isabelle [FR]/[FR] (UsOnly)
Inventors
  • DUVILLARD, Sylvain
  • DELBAERE, Isabelle
Agents
  • VAN OUDHEUSDEN-PERSET, Laure
Priority Data
03300273.419.12.2003EP
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) INTEGRATED CIRCUIT CLOCK DISTRIBUTION
(FR) DISTRIBUTION D'HORLOGE PARMI DES CIRCUITS INTEGRES
Abstract
(EN)
A circuit is provided with a plurality of interconnected logic blocks, a main clock generator for distributing a reference clock signal to the logic blocks. Each logic block in the circuit comprises a local clock generator that generates a set of synchronized local clock signals from the reference clock signal for further provision to respective elements of the logic block. In such a circuit, a phase shift is introduced between a set of local clock signals of a first block and a set of local clock signals of a second block.
(FR)
Le circuit décrit comprend une pluralité de blocs logiques interconnectés et un générateur principal d'horloge pour distribuer un signal d'horloge de référence parmi les blocs logiques. Chaque bloc logique dans le circuit comprend un générateur d'horloge local qui génère un ensemble de signaux d'horloge locaux synchronisés sur la base du signal d'horloge de référence et le fournit aux éléments respectifs du bloc logique. Dans ce circuit, un déphasage est introduit entre un ensemble de signaux d'horloge locaux d'un premier bloc et un ensemble de signaux d'horloge locaux d'un deuxième bloc.
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