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1. (WO2005057658) METHOD FOR MANUFACTURING THIN FILM INTEGRATED CIRCUIT DEVICE, NONCONTACT THIN FILM INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND IDTAG AND COIN INCLUDING THE NONCONTACT THIN FILM INTEGRATED CIRCUIT DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2005/057658 International Application No.: PCT/JP2004/018978
Publication Date: 23.06.2005 International Filing Date: 14.12.2004
IPC:
G06K 19/077 (2006.01) ,H01L 21/336 (2006.01) ,H01L 21/84 (2006.01) ,H01L 27/12 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
K
RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
19
Record carriers for use with machines and with at least a part designed to carry digital markings
06
characterised by the kind of the digital marking, e.g. shape, nature, code
067
Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards
07
with integrated circuit chips
077
Constructional details, e.g. mounting of circuits in the carrier
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
84
the substrate being other than a semiconductor body, e.g. being an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 398, Hase, Atsugi-shi Kanagawa 2430036, JP (AllExceptUS)
YAMAZAKI, Shunpei [JP/JP]; JP (UsOnly)
KOMORI, Miho [JP/JP]; JP (UsOnly)
SATOU, Yurika [JP/JP]; JP (UsOnly)
HOSOKI, Kazue [JP/JP]; JP (UsOnly)
OGITA, Kaori [JP/JP]; JP (UsOnly)
Inventors:
YAMAZAKI, Shunpei; JP
KOMORI, Miho; JP
SATOU, Yurika; JP
HOSOKI, Kazue; JP
OGITA, Kaori; JP
Priority Data:
2003-41731715.12.2003JP
Title (EN) METHOD FOR MANUFACTURING THIN FILM INTEGRATED CIRCUIT DEVICE, NONCONTACT THIN FILM INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND IDTAG AND COIN INCLUDING THE NONCONTACT THIN FILM INTEGRATED CIRCUIT DEVICE
(FR) PROCEDE DE FABRICATION D'UN DISPOSITIF DE CIRCUIT INTEGRE A FILM MINCE, DISPOSITIF DE CIRCUIT INTEGRE A FILM MINCE SANS CONTACT ET PROCEDE DE FABRICATION DUDIT DISPOSITIF ET ETIQUETTE ID ET PIECE COMPRENANT LE DISPOSITIF DE CIRCUIT INTEGRE A FILM MINCE SANS CONTACT
Abstract:
(EN) To provide a thin film integrated circuit which is mass produced at low cost, a method for manufacturing a thin film integrated circuit according to the invention includes the steps of: forming a peel-off layer over a substrate; forming a base film over the peel-off layer; forming a plurality of thin film integrated circuits over the base film; forming a groove at the boundary between the plurality of thin film integrated circuits; and introducing a gas or a liquid containing halogen fluoride into the groove, thereby removing the peel-off layer; thus, the plurality of thin film integrated circuits are separated from each other.
(FR) Afin d'obtenir un circuit intégré à film mince à production massive et à faible coût, on met en oeuvre un procédé de fabrication d'un circuit intégré à film mince consistant à: former une couche pelable sur un substrat; former un film de base sur ladite couche; former une pluralité de circuits intégrés à film mince sur le film de base; former une rainure à la limite entre la pluralité de circuits intégrés à film mince; et introduire un gaz ou un liquide contenant un fluorure d'halogène dans la rainure, ce qui a pour effet de retirer la couche pelable; la pluralité de circuits intégrés à film mince sont alors séparés.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)