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Machine translation
1. (WO2005039047) VERNIER CIRCUIT FOR FINE CONTROL OF SAMPLE TIME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2005/039047    International Application No.:    PCT/US2004/032876
Publication Date: 28.04.2005 International Filing Date: 05.10.2004
Chapter 2 Demand Filed:    09.08.2005    
IPC:
H03H 11/26 (2006.01)
Applicants: ATMEL CORPORATION [US/US]; 2325 Orchard Parkway, San Jose, CA 95131 (US) (For All Designated States Except US)
Inventors: FAGAN, John, L.; (US).
BOSSARD, Mark, A.; (US).
COHEN, Daniel, S.; (US)
Agent: SCHNECK, Thomas; Schneck & Schneck, P.O. Box 2-E, San Jose, CA 95109-0005 (US)
Priority Data:
60/510,737 10.10.2003 US
10/837,478 29.04.2004 US
Title (EN) VERNIER CIRCUIT FOR FINE CONTROL OF SAMPLE TIME
(FR) CIRCUIT VERNIER POUR REGLAGE FIN DE TEMPS ECHANTILLON
Abstract: front page image
(EN)A vernier time shifting circuit 100 is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit 100 allows shifting the signal in small steps to allow for optimal sampling. Various amounts of delay of the time-shifted signal are available at a plurality of output delay taps 113.
(FR)L'invention concerne un circuit vernier de décalage de temps (100) qui permet d'exécuter un réglage fin sur un signal d'horloge et/ou un signal de données pour compenser les fluctuations dues au système ou à d'autres variations dans des parties invariables indépendamment du temps de la puce. D'autres exemples de variations sont les différences de traitement, de température ou de tension. Le circuit vernier de décalage de temps (100) permet de décaler progressivement le signal et de favoriser ainsi un échantillonnage optimal. Divers degrés de retard du signal décalé dans le temps sont possibles dans une pluralité de branchements de retard de sortie (113).
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)