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Pub. No.: WO/2005/038928 International Application No.: PCT/JP2004/015018
Publication Date: 28.04.2005 International Filing Date: 12.10.2004
IPC:
H01L 21/316 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
314
Inorganic layers
316
composed of oxides or glassy oxides or oxide-based glass
Applicants: SUGAWARA, Takuya[JP/US]; US (UsOnly)
MIYATANI, Kotaro[JP/JP]; JP (UsOnly)
SHIMOMURA, Kouji[JP/JP]; JP (UsOnly)
NAKAMURA, Genji[JP/JP]; JP (UsOnly)
TOKYO ELECTRON LIMITED[JP/JP]; 3-6, Akasaka 5-chome, Minato-ku Tokyo 1078481, JP (AllExceptUS)
Inventors: SUGAWARA, Takuya; US
MIYATANI, Kotaro; JP
SHIMOMURA, Kouji; JP
NAKAMURA, Genji; JP
Agent: YAMAKAWA, Masaki; c/o Yamakawa International Patent Office, 8th Floor, Shuwa-Tameike Building, 4-2, Nagatacho 2-chome, Chiyoda-ku Tokyo 1000014, JP
Priority Data:
2003-35820717.10.2003JP
Title (EN) METHOD FOR MANUFACTURING TRANSISTOR
(FR) PROCEDE DE FABRICATION DE TRANSISTOR
(JA) トランジスタの製造方法
Abstract:
(EN) Using TDEAH as the source gas of hafnium, TDMAS as the source gas of silicon and an oxygen gas as the oxygen supply source, hafnium silicate is deposited on a major surface of a silicon substrate (101) by a chemical vapor deposition method under a process pressure of 100Pa, thereby forming an insulating film (102). Deposition is continued while changing the process pressure to a relatively high pressure of 800 Pa, thereby forming a gate insulating film (103).
(FR) Au moyen de TDEAH en tant que gaz source d'hafnium, de TDMAS en tant que gaz source de silicium et d'oxygène gazeux en tant que source d'alimentation en oxygène, on dépose du silicate d'hafnium sur une surface principale d'un substrat en silicium (101), par un procédé de dépôt chimique en phase vapeur à une pression de traitement de 100 Pa, et on forme ainsi un film isolant (102). On continue le dépôt en changeant la pression de traitement, de manière qu'elle soit portée à une pression relativement élevée de 800 PA, et on forme ainsi un film d'isolation de grille (103).
(JA)  シリコン基板101の主表面に、TDEAHをハフニウムのソースガスとし、TDMASをシリコンのソースガスとし、酸素供給源として酸素ガスを用いた化学的気相成長法により、プロセス圧力が100Paの状態でハフニウムシリケートを堆積し、絶縁膜102が形成された状態とする。引き続き、プロセス圧力を800Paと比較的高圧の状態に変更して堆積を継続しゲート絶縁膜103が形成された状態とする。
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)