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1. (WO2005036641) METHOD FOR SEPARATELY OPTIMIZING THIN GATE DIELECTRIC OF PMOS AND NMOS TRANSISTORS WITHIN THE SAME SEMICONDUCTOR CHIP AND DEVICE MANUFACTURED THEREBY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2005/036641    International Application No.:    PCT/US2004/028878
Publication Date: 21.04.2005 International Filing Date: 07.09.2004
IPC:
H01L 21/8238 (2006.01)
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road, Armonk, NY 10504 (US) (For All Designated States Except US).
CHOU, Anthony, I. [US/US]; (US) (For US Only).
FURUKAWA, Toshiharu [JP/US]; (US) (For US Only).
VAREKAMP, Patrick, R. [US/US]; (US) (For US Only).
SLEIGHT, Jeffrey, W. [US/US]; (US) (For US Only).
SEKIGUCHI, Akihisa [JP/US]; (US) (For US Only)
Inventors: CHOU, Anthony, I.; (US).
FURUKAWA, Toshiharu; (US).
VAREKAMP, Patrick, R.; (US).
SLEIGHT, Jeffrey, W.; (US).
SEKIGUCHI, Akihisa; (US)
Agent: SCHNURMANN, Daniel, H.; IBM Corporation, Dept- 18G., Building 300/482, 2070 Route 52, Hopewell Junction, NY 12533 (US)
Priority Data:
10/605,110 09.09.2003 US
Title (EN) METHOD FOR SEPARATELY OPTIMIZING THIN GATE DIELECTRIC OF PMOS AND NMOS TRANSISTORS WITHIN THE SAME SEMICONDUCTOR CHIP AND DEVICE MANUFACTURED THEREBY
(FR) PROCEDE D'OPTIMISATION SEPAREE DE DIELECTRIQUE DE GRILLE MINCE POUR TRANSISTORS PMOS ET NMOS DANS LA MEME PUCE A SEMI-CONDUCTEUR, ET DISPOSITIF AINSI FABRIQUE
Abstract: front page image
(EN)A method of forming CMOS semiconductor (10) materials with PFET (16) and NFET (14) areas formed on a semiconductor substrate (12), covered respectively with a PFET (16) and NFET (14) gate dielectric layers composed of silicon oxide and different degrees of nitridation (18D and 18E) thereof. Provide a silicon substrate (12) with a PFET (16) area and an NFET (14) area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer (42) above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric I ayer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer (40) above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer (40) and the PFET gate dielectric layer (42) can have the same thickness.
(FR)L'invention concerne un procédé de fabrication de matériaux à semi-conducteur CMOS, avec zones PFET et NFET établies sur un substrat à semi-conducteur, que l'on recouvre respectivement de couches diélectriques de grille PFET et NFET en oxyde de silicium, avec différents degrés de nitruration. L'invention concerne un substrat en silicium à zones PFET et NFET recouvertes de couches d'oxyde de grille PFET et NFET. La nitruration de la couche d'oxyde de grille PFET au-dessus de la zone PFET permet de former la couche diélectrique de grille PFET au-dessus de la zone PFET, selon une première concentration d'atomes d'azote dans la couche diélectrique de grille PFET au-dessus de la zone PFET. La nitruration de la couche d'oxyde de grille NFET permet de former la couche diélectrique de grille NFET au-dessus de la zone NFET, selon une concentration d'atomes d'azote différente de la première concentration. Les deux couches diélectriques de grille NFET et PFET peuvent avoir la même épaisseur.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)