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Machine translation
1. (WO2005031565) PROCESSOR WITH DEMAND-DRIVEN CLOCK THROTTLING FOR POWER REDUCTION
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2005/031565    International Application No.:    PCT/US2003/026531
Publication Date: 07.04.2005 International Filing Date: 26.08.2003
Chapter 2 Demand Filed:    06.09.2004    
IPC:
G06F 1/04 (2006.01), G06F 1/32 (2006.01), G06F 9/38 (2006.01)
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road, Armonk, NY 10504 (US) (For All Designated States Except US).
BOSE, Pradip [US/US]; (US) (For US Only).
CITRON, Daniel, M. [IL/US]; (US) (For US Only).
COOK, Peter, W. [US/US]; (US) (For US Only).
EMMA, Philip, G. [US/US]; (US) (For US Only).
JACOBSON, Hans, M. [SE/US]; (US) (For US Only).
KUDVA, Prabhakar, N. [IN/US]; (US) (For US Only).
SCHUSTER, Stanley, E. [US/US]; (US) (For US Only).
RIVERS, Jude, A. [US/US]; (US) (For US Only).
ZYUBAN, Victor, V. [RU/US]; (US) (For US Only)
Inventors: BOSE, Pradip; (US).
CITRON, Daniel, M.; (US).
COOK, Peter, W.; (US).
EMMA, Philip, G.; (US).
JACOBSON, Hans, M.; (US).
KUDVA, Prabhakar, N.; (US).
SCHUSTER, Stanley, E.; (US).
RIVERS, Jude, A.; (US).
ZYUBAN, Victor, V.; (US)
Agent: PERCELLO, Louis, J.; International Business Machines Corporation, T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598 (US)
Priority Data:
Title (EN) PROCESSOR WITH DEMAND-DRIVEN CLOCK THROTTLING FOR POWER REDUCTION
(FR) PROCESSEUR A RESTRICTION D'HORLOGE PILOTEE PAR LA DEMANDE POUR REDUCTION DE PUISSANCE
Abstract: front page image
(EN)A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.
(FR)Un circuit intégré synchrone tel qu'un processeur scalaire ou un processeur super-scalaire. Les composants circuits ou les unités sont pilotés par une horloge système commune et synchronisés par elle. Pour deux au moins des unités ainsi pilotées, il s'agit d'étages registres multiples, notamment des étages pipeline. Pour chaque unité ainsi pilotée, une horloge locale combine les signaux d'horloge système commune et l'état de différé de l'une au moins des autres unités pour augmenter ou diminuer la fréquence d'horloge des registres.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)