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1. WO2005022631 - SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

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Publication Number WO/2005/022631
Publication Date 10.03.2005
International Application No. PCT/JP2004/012588
International Filing Date 25.08.2004
IPC
H01L 23/12 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
H01L 29/76 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
CPC
H01L 21/76898
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76898formed through a semiconductor substrate
H01L 2224/02372
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
023Redistribution layers [RDL] for bonding areas
0237Disposition of the redistribution layers
02372connecting to a via connection in the semiconductor or solid-state body
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/13024
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
1302Disposition
13024the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
H01L 2224/451
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
45099Material
451with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
Applicants
  • 株式会社フジクラ FUJIKURA LTD. [JP]/[JP] (AllExceptUS)
  • オリンパス株式会社 OLYMPUS CORPORATION [JP]/[JP] (AllExceptUS)
  • 山本 敏 YAMAMOTO, Satoshi [JP]/[JP] (UsOnly)
  • 末益 龍夫 SUEMASU, Tatsuo [JP]/[JP] (UsOnly)
  • 平船 さやか HIRAFUNE, Sayaka [JP]/[JP] (UsOnly)
  • 磯川 俊彦 ISOKAWA, Toshihiko [JP]/[JP] (UsOnly)
  • 塩谷 浩一 SHIOTANI, Koichi [JP]/[JP] (UsOnly)
  • 松本 一哉 MATSUMOTO, Kazuya [JP]/[JP] (UsOnly)
Inventors
  • 山本 敏 YAMAMOTO, Satoshi
  • 末益 龍夫 SUEMASU, Tatsuo
  • 平船 さやか HIRAFUNE, Sayaka
  • 磯川 俊彦 ISOKAWA, Toshihiko
  • 塩谷 浩一 SHIOTANI, Koichi
  • 松本 一哉 MATSUMOTO, Kazuya
Agents
  • 志賀 正武 SHIGA, Masatake
Priority Data
2003-30484828.08.2003JP
2003-41961317.12.2003JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
(FR) BOITIER DE SEMI-CONDUCTEUR ET PROCEDE DE PRODUCTION ASSOCIE
(JA) 半導体パッケージおよびその製造方法
front page image
Abstract
(EN) A semiconductor package includes a semiconductor element having a circuit element arranged on a first surface of a semiconductor substrate; an external wiring region arranged on a second surface of the semiconductor substrate; a support substrate arranged on the first surface of the semiconductor substrate; an electrode pad arranged on the first surface of the semiconductor substrate; and a through electrode reaching from the electrode pad to the second surface of the semiconductor substrate.
(FR) L'invention concerne un boîtier de semi-conducteur qui comprend un élément semi-conducteur possédant un élément de circuit disposé sur une première surface d'un substrat semi-conducteur ; une zone de câblage externe disposée sur une deuxième surface du substrat semi-conducteur ; un substrat de support disposé sur la première surface du substrat semi-conducteur ; une plaquette d'électrode disposée sur la première surface du substrat semi-conducteur ; et une électrode traversante qui atteint la deuxième surface du substrat semi-conducteur depuis la plaquette d'électrode.
(JA) この発明の半導体パッケージは、半導体基板の一方の面に回路素子が設けられた半導体素子と、前記半導体基板の他方の面に設けられた外部配線領域と、前記半導体基板の一方の面に配置された支持基板と、前記半導体基板の一方の面に配置された電極パッドと、前記電極パッドから前記半導体基板の他方の面に到達する貫通電極と、を有する。
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