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Machine translation
1. (WO2005015534) DELAY TIME CORRECTION CIRCUIT, VIDEO DATA PROCESSING CIRCUIT, AND FLAT DISPLAY APPARATUS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2005/015534    International Application No.:    PCT/JP2004/011029
Publication Date: 17.02.2005 International Filing Date: 27.07.2004
IPC:
G09G 3/36 (2006.01)
Applicants: SONY CORPORATION [JP/JP]; 7-35, Kitashinagawa 6-chome, Shinagawa-ku, Tokyo 1410001 (JP) (For All Designated States Except US).
MURASE, Masaki [JP/JP]; (JP) (For US Only).
NAKAJIMA, Yoshiharu [JP/JP]; (JP) (For US Only).
KIDA, Yoshitoshi [JP/JP]; (JP) (For US Only)
Inventors: MURASE, Masaki; (JP).
NAKAJIMA, Yoshiharu; (JP).
KIDA, Yoshitoshi; (JP)
Agent: TADA, Shigenori; TADA Patent Office, 501, Sutera Building, 45-2, Higashiikebukuro 2-chome, Toshima-ku, Tokyo 1700013 (JP)
Priority Data:
2003-280583 28.07.2003 JP
2003-347803 07.10.2003 JP
Title (EN) DELAY TIME CORRECTION CIRCUIT, VIDEO DATA PROCESSING CIRCUIT, AND FLAT DISPLAY APPARATUS
(FR) CIRCUIT DE CORRECTION DE DELAI D'ATTENTE, CIRCUIT DE TRAITEMENT DE DONNEES VIDEO ET APPAREIL D'AFFICHAGE PLAT
(JA) 遅延時間補正回路、ビデオデータ処理回路及びフラットディスプレイ装置
Abstract: front page image
(EN)The present invention is applicable to a liquid crystal display apparatus in which a driver circuit is integrally formed on, for example, an insulating substrate. At a predetermined timing during a quiescent period (T2) when the liquid crystal display apparatus is maintained at a certain logic level, a dummy data (DD) is inserted into an input data (D1) to enforcedly change the logic level of the input data (D1), whereby any variation of the delay time in the logic circuit using TFT and the like can be effectively avoided.
(FR)La présente invention concerne un appareil d'affichage à cristaux liquides sur lequel est intégré un circuit pilote, par exemple un substrat d'isolation. A un moment prédéfini lors d'une période de repos (T2), lorsque l'appareil d'affichage à cristaux liquides est maintenu à un certain niveau logique, une donnée fictive (DD) est insérée dans une donnée d'entrée (D1) afin de forcer la modification du niveau logique de la donnée d'entrée (D1), ce qui permet d'éviter efficacement toute variation du délai d'attente dans le circuit logique utilisant des TFT ou similaires.
(JA)not available
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)