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1. (WO2005013350) METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR AND DEVICE WITH A BIPOLAR TRANSISTOR
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2005/013350 International Application No.: PCT/IB2004/051292
Publication Date: 10.02.2005 International Filing Date: 26.07.2004
IPC:
H01L 21/331 (2006.01) ,H01L 29/417 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328
Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
33
the devices comprising three or more electrodes
331
Transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
Applicants:
NEUILLY, Francois, I. [FR/BE]; NL (UsOnly)
DONKERS, Johannes, J., T., M. [NL/NL]; NL (UsOnly)
AKSEN, Eyup [FR/BE]; NL (UsOnly)
MELAI, Joost [NL/BE]; NL (UsOnly)
FURUKAWA, Yukiko [JP/BE]; NL (UsOnly)
KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL (AllExceptUS)
Inventors:
NEUILLY, Francois, I.; NL
DONKERS, Johannes, J., T., M.; NL
AKSEN, Eyup; NL
MELAI, Joost; NL
FURUKAWA, Yukiko; NL
Agent:
ELEVELD, Koop, J.; Prof. Holstlaan 6 NL-5656 AA Eindhoven, NL
Priority Data:
03102405.201.08.2003EP
Title (EN) METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR AND DEVICE WITH A BIPOLAR TRANSISTOR
(FR) METHODE DE FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR AVEC UN TRANSISTOR BIPOLAIRE ET DISPOSITIF AVEC UN TRANSISTOR BIPOLAIRE
Abstract:
(EN) The invention relates to the manufacturing of a bipolar transistor device (10) in which the emitter is formed using a polycrystalline silicon region (14) which is prevent in a window in an insulating layer (13) and which extends laterally over said insulating layer (13). The silicon region (14) as well as another silicon region (12) bordering the stack of insulating region (13) and silicon region (14) are silicided by means of a metal layer (16) deposited over the structure. The sideface of the stack is provided with means to avoid bridging of the silicides (17) to be formed. According to the invention the means to prevent bridging of the silicides to be formed comprises that the side face of the stack is structured in such a way that the distance between the upper surface of the silicon region (14) and the upper surface the other silicon region (12) along the surface of the side face of the stack is made longer than the total thickness of the insulating layer (13) and the semiconductor layer (14). Through the increased path by either a positive or negative slope of the side face of the stack, the bridging of silicides is avoided. Preferred embodiments relate to how the side face of the stack is structured.
(FR) L'invention concerne la fabrication d'un dispositif (10) à transistor bipolaire dont l'émetteur est formé en utilisant une zone (14) en silicium polycristallin présente dans une fenêtre dans une couche isolante (13) et qui s'étend latéralement sur la couche isolante (13). La zone en silicium (14) et une autre zone en silicium (12) adjacente à la pile formée par la zone isolante (13) et par la zone en silicium (14) sont siliciurées au moyen d'une couche métallique (16) déposée sur la structure. La face latérale de la pile comprend des moyens pour éviter le pontage des siliciures (17) devant être formés. Selon l'invention, les moyens utilisés pour éviter le pontage des siliciures devant être formés comprennent la structuration de la face latérale de la pile de telle sorte que la distance entre la surface supérieure de la zone en silicium (14) et la surface supérieure de l'autre zone en silicium (12) le long de la surface de la face latérale de la pile soit plus longue que l'épaisseur totale de la couche isolante (13) et de la couche semi-conductrice (14). Le pontage des siliciures est évité en ce que la voie est allongée par une pente positive ou négative de la face latérale de la pile. Les modes préférentiels de réalisation concernent la façon de structurer la face latérale de la pile.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)