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1. (WO2005010995) ELECTRONIC ELEMENT, INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THE SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2005/010995 International Application No.: PCT/JP2003/016172
Publication Date: 03.02.2005 International Filing Date: 17.12.2003
IPC:
H01L 51/30 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
05
specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
30
Selection of materials
Applicants: HIRAKATA, Masaki[JP/JP]; JP (UsOnly)
ISOZAKI, Takashi[JP/JP]; JP (UsOnly)
KISHI, Kentaro[JP/JP]; JP (UsOnly)
SHIGEMATSU, Taishi[JP/JP]; JP (UsOnly)
WATANABE, Miho[JP/JP]; JP (UsOnly)
MANABE, Chikara[JP/JP]; JP (UsOnly)
ANAZAWA, Kazunori[JP/JP]; JP (UsOnly)
WATANABE, Hiroyuki[JP/JP]; JP (UsOnly)
OKADA, Shinsuke[JP/JP]; JP (UsOnly)
OOMA, Shigeki[JP/JP]; JP (UsOnly)
FUJI XEROX CO., LTD.[JP/JP]; 17-22, Akasaka 2-chome Minato-ku, Tokyo 107-0052, JP (AllExceptUS)
Inventors: HIRAKATA, Masaki; JP
ISOZAKI, Takashi; JP
KISHI, Kentaro; JP
SHIGEMATSU, Taishi; JP
WATANABE, Miho; JP
MANABE, Chikara; JP
ANAZAWA, Kazunori; JP
WATANABE, Hiroyuki; JP
OKADA, Shinsuke; JP
OOMA, Shigeki; JP
Agent: NAKAMURA, Tomohiro ; 5th Floor, Central Shinbashi Bldg. 11-5, Nishi-shinbashi 2-chome Minato-ku, Tokyo 105-0003, JP
Priority Data:
2003-28037425.07.2003JP
Title (EN) ELECTRONIC ELEMENT, INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THE SAME
(FR) ELEMENT ELECTRONIQUE, CIRCUIT INTEGRE ET PROCEDE DE FABRICATION CORRESPONDANT
(JA) 電子素子、集積回路およびその製造方法
Abstract:
(EN) An electronic element having a transport layer exhibiting excellent semiconductor characteristics while reducing the environmental load and formed, on the surface of a basic body, of a carbon nanotube structure layer where a plurality of carbon nanotubes constitute a crosslinked mesh structure. A process for fabricating the electronic element is also provided.
(FR) Cette invention se rapporte à un élément électronique comprenant une couche de transport présentant d'excellentes caractéristiques semi-conductrices, tout en réduisant la charge sur l'environnement, et comportant, sur la surface d'un corps de base, une couche à structure de nanotubes en carbone, dont plusieurs nanotubes carbone constituent une structure en treillis réticulée. Un procédé de fabrication de cet élément électronique est également présenté.
(JA) 本発明は、基体の表面に、少なくとも、複数のカーボンナノチューブが相互に架橋した網目構造を構成するカーボンナノチューブ構造体層により構成された輸送層を備える構成により、環境負荷が少なく、半導体特性に優れた輸送層を備えた電子素子を提供し、加えてその製造方法を提供するものである。
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)