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1. (WO2005010946) DEPOSITION OF SiGe ON SILICON-ON-INSULATOR STRUCTURES AND BULK SUBSTRATES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2005/010946 International Application No.: PCT/US2004/023505
Publication Date: 03.02.2005 International Filing Date: 21.07.2004
IPC:
H01L 21/76 (2006.01) ,H01L 21/20 (2006.01) ,C30B 1/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
C CHEMISTRY; METALLURGY
30
CRYSTAL GROWTH
B
SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
1
Single-crystal growth directly from the solid state
Applicants: BAUER, Matthias[DE/DE]; DE (UsOnly)
ASM AMERICA, INC.[US/US]; 3440 East University Drive Phoenix, AZ 85034-7200, US (AllExceptUS)
Inventors: BAUER, Matthias; DE
Agent: DELANEY, Karoline, A.; 2040 Main Street Fourteenth Floor Irvine, CA 92614, US
Priority Data:
60/489,69123.07.2003US
Title (EN) DEPOSITION OF SiGe ON SILICON-ON-INSULATOR STRUCTURES AND BULK SUBSTRATES
(FR) DEPOT DE SIGE SUR DES STRUCTURES A SILICIUM SUR ISOLANT ET SUR DES SUBSTRATS MASSIFS
Abstract:
(EN) Methods are provided for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects. Amorphous SiGe layers are deposited by CVD from trisilane and GeH4. The amorphous SiGe layers are recrystallized over silicon by melt or solid phase epitaxy (SPE) processes. The melt processes preferably also cause diffusion of germanium to dilute the overall germanium content and essentially consume the silicon overlying the insulator. The SPE process can be conducted with or without diffusion of germanium into the underlying silicon, and so is applicable to SOI as well as conventional semiconductor substrates.
(FR) L'invention concerne des procédés de production de structures à SiGe sur isolant et de formation de couches de SiGe relaxé sur du silicium avec une minimisation des défauts. Les couches de SiGe amorphe sont déposées selon un procédé de dépôt chimique en phase vapeur à partir de trisilane et de GeH4. Les couches SiGe amorphe sont recristallisées sur le silicium selon un procédé par fusion ou par épitaxie en phase solide. Le procédé par fusion entraîne, de préférence, également la diffusion du germanium, ce qui provoque la dilution de tout le germanium et, sensiblement, la consommation du silicium recouvrant l'isolant. Le procédé par épitaxie en phase solide peut être mis en oeuvre avec ou sans diffusion du germanium dans la couche de silicium sous-jacente et il peut être appliqué tant à des substrats du type silicium sur isolant qu'à des substrats semi-conducteurs classiques.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)